Patents by Inventor Plamen Vassilev Kolev

Plamen Vassilev Kolev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210343661
    Abstract: Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency ICs.
    Type: Application
    Filed: July 7, 2021
    Publication date: November 4, 2021
    Inventors: Plamen Vassilev Kolev, Anil Kumar Vemulapalli, Matthew Deig
  • Patent number: 11133272
    Abstract: Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency (RF) ICs.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 28, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Plamen Vassilev Kolev, Anil Kumar Vemulapalli, Matthew Deig
  • Patent number: 11094651
    Abstract: Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency (RF) ICs.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: August 17, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Plamen Vassilev Kolev, Anil Kumar Vemulapalli, Matthew Deig
  • Patent number: 10770391
    Abstract: A transistor may include a semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The channel region may have a source interface and a drain interface, and may be bounded by edges extending from the source interface to the drain interface on two boundaries between a field-sensitive semiconductor material and an isolation material. The transistor may further include an insulator layer on the channel region. The transistor may further include a gate on the insulator layer. The gate may have extensions beyond edges of the channel region. The extensions may substantially exceed a minimum specified value.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: September 8, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Plamen Vassilev Kolev, Michael Andrew Stuber, Lee-Wen Chen
  • Patent number: 10608124
    Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Fabio Alessio Marino, Narasimhulu Kanike, Plamen Vassilev Kolev, Qingqing Liang, Paolo Menegoli, Francesco Carobolante, Aristotele Hadjichristos
  • Patent number: 10600894
    Abstract: A Bipolar Junction Transistor (BJT) comprises an emitter, a collector, and a base between the emitter and the collector. The BJT also comprises an emitter contact on a first side of the BJT, a base contact on the first side of the BJT, and a collector contact on a second side of the BJT. The BJT further comprises a Deep Trench Isolation (DTI) region extending from the first side of the BJT to the second side of the BJT.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Plamen Vassilev Kolev, Peter Graeme Clarke
  • Publication number: 20200013884
    Abstract: A Bipolar Junction Transistor (BJT) comprises an emitter, a collector, and a base between the emitter and the collector. The BJT also comprises an emitter contact on a first side of the BJT, a base contact on the first side of the BJT, and a collector contact on a second side of the BJT. The BJT further comprises a Deep Trench Isolation (DTI) region extending from the first side of the BJT to the second side of the BJT.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Sinan GOKTEPELI, Plamen Vassilev KOLEV, Peter Graeme CLARKE
  • Publication number: 20190326401
    Abstract: In certain aspects, a silicon-on-insulator device comprises a back insulating layer and a semiconductor layer on the back insulating layer. The semiconductor layer includes a source region of a first conductive type having a front source surface and a back source surface, a channel region of a second conductive type have a front channel surface and a back channel surface, and a drain region of the first conductive type. The silicon-on-insulator device further comprises a gate insulating layer on the front channel surface of the channel region and a back silicidation layer on at least a portion of the back source surface and a portion of back channel surface.
    Type: Application
    Filed: April 20, 2018
    Publication date: October 24, 2019
    Inventors: Plamen Vassilev KOLEV, Sinan GOKTEPELI, Peter Graeme CLARKE
  • Publication number: 20190326448
    Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a semiconductor region, an insulative layer, a first terminal, and a first non-insulative region coupled to the first terminal, the insulative layer being disposed between the first non-insulative region and the semiconductor region. In certain aspects, the insulative layer is disposed adjacent to a first side of the semiconductor region. In certain aspects, the semiconductor device also includes a second terminal, and a first silicide layer coupled to the second terminal and disposed adjacent to a second side of the semiconductor region, the first side and the second side being opposite sides of the semiconductor region.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 24, 2019
    Inventors: Sinan GOKTEPELI, Fabio Alessio MARINO, Narasimhulu KANIKE, Plamen Vassilev KOLEV, Qingqing LIANG, Paolo MENEGOLI, Francesco CAROBOLANTE, Aristotele HADJICHRISTOS
  • Publication number: 20190304898
    Abstract: A transistor may include a semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The channel region may have a source interface and a drain interface, and may be bounded by edges extending from the source interface to the drain interface on two boundaries between a field-sensitive semiconductor material and an isolation material. The transistor may further include an insulator layer on the channel region. The transistor may further include a gate on the insulator layer. The gate may have extensions beyond edges of the channel region. The extensions may substantially exceed a minimum specified value.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Plamen Vassilev KOLEV, Michael Andrew STUBER, Lee-Wen CHEN
  • Publication number: 20190214506
    Abstract: A resistor may include a semiconductor layer having a source region, a drain region, and a channel region. The channel region may be between the source region and the drain region. The channel region may have a same polarity as the source region and the drain region. The resistor may further include a first inter-metal dielectric (IMD) layer on the channel region. The resistor may further include a front-side gate shield on the first IMD layer. The front-side gate shield may overlap the channel region.
    Type: Application
    Filed: January 8, 2018
    Publication date: July 11, 2019
    Inventors: Plamen Vassilev KOLEV, Sinan GOKTEPELI, Peter Graeme CLARKE
  • Patent number: 10326028
    Abstract: A resistor may include a semiconductor layer having a source region, a drain region, and a channel region. The channel region may be between the source region and the drain region. The channel region may have a same polarity as the source region and the drain region. The resistor may further include a first inter-metal dielectric (IMD) layer on the channel region. The resistor may further include a front-side gate shield on the first IMD layer. The front-side gate shield may overlap the channel region.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Plamen Vassilev Kolev, Sinan Goktepeli, Peter Graeme Clarke
  • Patent number: 10290579
    Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Plamen Vassilev Kolev, Michael Andrew Stuber, Richard Hammond, Shiqun Gu, Steve Fanelli
  • Publication number: 20180076137
    Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
    Type: Application
    Filed: November 8, 2017
    Publication date: March 15, 2018
    Inventors: Sinan GOKTEPELI, Plamen Vassilev KOLEV, Michael Andrew STUBER, Richard HAMMOND, Shiqun GU, Steve FANELLI
  • Patent number: 9847293
    Abstract: An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor dielectric layer may separate the first plate and the second plate. A backside metallization may be coupled to the first plate of the capacitor. A front-side metallization may be coupled to the second plate of the capacitor. The front-side metallization may be arranged distal from the backside metallization.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: December 19, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Plamen Vassilev Kolev, Michael Andrew Stuber, Richard Hammond, Shiqun Gu, Steve Fanelli
  • Patent number: 6057701
    Abstract: A system, methods and apparatus for determining the properties of electrically active imperfections in semiconductor materials by Deep Level Transient Spectroscopy (DLTS) are disclosed. Source-drain resistance of a field-effect transistor (FET) is compared with a reference resistor and the difference is applied through a feedback circuit to the gate. The obtained voltage transient compensates for the threshold voltage changes resulting from the emission of charges trapped by the imperfections during pulses applied to the gate and alternating with the action of the feedback circuit. Knowledge of the free charge carrier mobility is not necessary, and the intensity of the DLTS signal and the sensitivity of the measurement are area independent. Thereof, the method is advantageous for measurement of deep submicron FETs.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: May 2, 2000
    Inventor: Plamen Vassilev Kolev