Patents by Inventor Po-Chin NIEN
Po-Chin NIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230154762Abstract: A method of forming a semiconductor device is provided. The method includes forming a first film over an active region of a first side of a semiconductor substrate and a second film over a second side of the semiconductor substrate opposing to the first side of the semiconductor substrate; applying a chemical mechanical polishing to remove at least a portion of the second film; after the chemical mechanical polishing, forming a photoresist layer over the first film; and patterning the photoresist layer using an extreme ultraviolet radiation.Type: ApplicationFiled: May 9, 2022Publication date: May 18, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Wei Hu, Po-Chin Nien
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Publication number: 20220415665Abstract: A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. An impurity removal system removes debris and impurities from the slurry.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventors: Te-Chien HOU, Po-Chin NIEN, Chih Hung CHEN, Ying-Tsung CHEN, Kei-Wei CHEN
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Patent number: 11189497Abstract: A method includes forming a film over a substrate; increasing a surface roughness of the film; and planarizing the film using a first chemical mechanical planarization (CMP) process after increasing the surface roughness.Type: GrantFiled: May 17, 2019Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chin Nien, Gang Huang, William Weilun Hong
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Publication number: 20200365413Abstract: A method includes forming a film over a substrate; increasing a surface roughness of the film; and planarizing the film using a first chemical mechanical planarization (CMP) process after increasing the surface roughness.Type: ApplicationFiled: May 17, 2019Publication date: November 19, 2020Inventors: Po-Chin Nien, Gang Huang, William Weilun Hong
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Patent number: 10541139Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.Type: GrantFiled: March 24, 2016Date of Patent: January 21, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 10068988Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.Type: GrantFiled: January 2, 2018Date of Patent: September 4, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
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Publication number: 20180145152Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.Type: ApplicationFiled: January 2, 2018Publication date: May 24, 2018Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
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Patent number: 9941109Abstract: A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned.Type: GrantFiled: June 29, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9922837Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.Type: GrantFiled: March 2, 2016Date of Patent: March 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9871115Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.Type: GrantFiled: July 1, 2016Date of Patent: January 16, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
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Publication number: 20180005840Abstract: A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20180006134Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Inventors: William Weilun Hong, Po-Chin Nien, Ying-Tsung Chen
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Publication number: 20170278712Abstract: A method of forming a semiconductor device includes forming fins on a substrate, depositing a gate layer having a first material on the fins, and depositing a sacrificial layer having a second material on the gate layer. The method further includes removing a first portion of the sacrificial layer using a first slurry or etchant having a first selectivity of second material to first material. The method further includes removing a first portion of the gate layer and a second portion of the sacrificial layer using a second slurry or etchant having a second selectivity of second material to first material to form a planarized gate layer. The first selectivity is greater than the second selectivity. An example benefit includes reduced dependency of the gate layer planarization process on underlying structure density and reduced variation in thickness of the gate layer on device structures across a wafer.Type: ApplicationFiled: March 24, 2016Publication date: September 28, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20170256414Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.Type: ApplicationFiled: March 2, 2016Publication date: September 7, 2017Inventors: Chih-Wen Liu, Che-Hao Tu, Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9721831Abstract: A method includes forming a plurality of first semiconductor fins and a plurality of second semiconductor fins in a substrate, depositing a gate electrode layer over the substrate, wherein upper portions of the plurality of first semiconductor fins and the plurality of second semiconductor fins are embedded in the gate electrode layer, depositing a reverse film over the gate electrode layer and applying a chemical mechanical polish process to the reverse film and the gate electrode layer, wherein during the step of applying the chemical mechanical polish process, depositing a slurry between a polishing pad and the reverse film, and wherein a slurry selectivity ratio of the gate electrode layer to the reverse film is greater than 1.Type: GrantFiled: December 3, 2015Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20170162432Abstract: A method includes forming a plurality of first semiconductor fins and a plurality of second semiconductor fins in a substrate, depositing a gate electrode layer over the substrate, wherein upper portions of the plurality of first semiconductor fins and the plurality of second semiconductor fins are embedded in the gate electrode layer, depositing a reverse film over the gate electrode layer and applying a chemical mechanical polish process to the reverse film and the gate electrode layer, wherein during the step of applying the chemical mechanical polish process, depositing a slurry between a polishing pad and the reverse film, and wherein a slurry selectivity ratio of the gate electrode layer to the reverse film is greater than 1.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
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Patent number: 9354198Abstract: A calibration method for blood glucose of blood sample comprises the following steps: applying a first voltage to a blood sample to obtain an original level of blood glucose of the blood sample; applying a second voltage to a blood sample to obtain a hematocrit index of the blood sample; and processing the hematocrit index and calibrating the original level of blood glucose of the blood sample. The absolute value of the first voltage is lower than 1 volt and is not equal to 0 volt. The absolute value of the second voltage is higher than or equal to 1 volt. A sensing current corresponding to the original blood level and the hematocrit index corresponding to blood sample are obtained by applying at least two-stage voltages in the specific range to the blood sample, thereby calibrating the original blood glucose according to the hematocrit index.Type: GrantFiled: April 25, 2013Date of Patent: May 31, 2016Assignee: DELBio, Inc.Inventors: Po-Chin Nien, Cheng-Chuan Chen, Chien-Yu Yin, Chi-Yan Chen
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Publication number: 20150034499Abstract: A determination method is provided. The determination method is performed for a biochemistry detection strip which includes first and second electrodes and a reaction area coupled to the first and second electrodes. The determination method includes steps of: disposing a to-be-detected object in the reaction area; applying a first voltage to the reaction area through the first and second electrodes to obtain a first value; stopping applying the first voltage to the reaction area for a first period; applying a second voltage to the reaction area through the first and second electrodes to obtain a second value; stopping applying the second voltage to the reaction area for a second period; and obtaining a determination index, which represents a filling situation of the to-be-detected object in the reaction area, according to the first and second values. Polarities of the first and second voltages are inverse to each other.Type: ApplicationFiled: July 31, 2014Publication date: February 5, 2015Inventors: Miao-Ju YEN, Po-Chin NIEN, Chi-Yan CHEN, Bo-Jiun SHEN
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Publication number: 20130334064Abstract: A calibration method for blood glucose of blood sample comprises the following steps: applying a first voltage to a blood sample to obtain an original level of blood glucose of the blood sample; applying a second voltage to a blood sample to obtain a hematocrit index of the blood sample; and processing the hematocrit index and calibrating the original level of blood glucose of the blood sample. The absolute value of the first voltage is lower than 1 volt and is not equal to 0 volt. The absolute value of the second voltage is higher than or equal to 1 volt. A sensing current corresponding to the original blood level and the hematocrit index corresponding to blood sample are obtained by applying at least two-stage voltages in the specific range to the blood sample, thereby calibrating the original blood glucose according to the hematocrit index.Type: ApplicationFiled: April 25, 2013Publication date: December 19, 2013Applicant: DELBIO, INC.Inventors: Po-Chin NIEN, Cheng-Chuan CHEN, Chien-Yu YIN, Chi-Yan CHEN