Patents by Inventor Po-Chun Chen

Po-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11470001
    Abstract: The following description is directed to configuring gateways in computer networks. For example, a method includes receiving a first request from a client associated with a configurable network. The first request can request associating a set of network addresses assigned to the configurable network to a gateway. A second request can be received from a client associated with the gateway. The second request can request accepting the association of the first request. It can be determined that the set of network addresses do not overlap with a network address space that is accessible using the gateway. Routing information can be generated for the gateway. The generated routing information can be used to configure the gateway for forwarding network packets between the client private network and the configurable network.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: October 11, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Po-Chun Chen, Sanjay Arunkumar Bhal, James Michael Lamanna, Kim Thanh Do, Justin Thomas Smith
  • Patent number: 11389644
    Abstract: A flexible thin film metal oxide electrode fabrication methods and devices are provided and illustrated with thin film polyimide electrode formation and IrOx chemical bath deposition. Growth factors of the deposited film such as film thickness, deposition rate and quality of crystallites can be controlled by varying the solution pH, temperature and component concentrations of the bath. The methods allow for selective deposition of IrOx on a flexible substrate (e.g. polyimide electrode) where the IrOx will only coat onto an exposed metal area but not the entire device surface. This feature enables the bath process to coat the IrOx onto every individual electrode in one batch, and to ensure electrical isolation between channels. The ability to perform selective deposition, pads for external connections will not have IrOx coverage that would otherwise interfere with a soldering/bumping process.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: July 19, 2022
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Wentai Liu, Chih-Wei Chang, Pu-Wei Wu, Chung-Yu Wu, Po-Chun Chen, Tsai-Wei Chung
  • Publication number: 20220216629
    Abstract: The present invention discloses an electrical connector and an electrical connector assembly. The electrical connector includes a circuit board, a connection port, and an insulating member. The circuit board has a conductive region, located on a surface of the circuit board. The connection port is arranged on the surface of the circuit board, and the connection port is electrically connected to the circuit board. The insulating member is arranged on the circuit board, and surrounds an outer periphery of the connection port. The insulating member includes a metal layer, arranged on an outer surface of the insulating member.
    Type: Application
    Filed: October 22, 2021
    Publication date: July 7, 2022
    Inventors: Ho-Ching HUANG, Chien-Hao HSU, Chyi-Nan CHEN, Chuan-Yuan LIN, Po-Chun CHEN
  • Patent number: 11231750
    Abstract: A shockproof element is applied to an electronic element. The shockproof element includes a first elastic portion, a second elastic portion and a connecting portion. The first elastic portion defines an opening. The second elastic portion is disposed corresponding to the first elastic portion. The second elastic portion includes a hollow column. The hollow column extends from the second elastic portion into the opening of the first elastic portion. The hollow column can fix the electronic element, and the first elastic portion and the second elastic portion jointly hold the electronic element. The connecting portion connects to the first elastic portion and the second elastic portion. An electronic device, which includes the shockproof element, the electronic element, a first housing and a second housing, is also provided.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: January 25, 2022
    Assignee: Pegatron Corporation
    Inventors: Chiao-Yi Lin, Po-Chun Chen
  • Patent number: 11182636
    Abstract: A method and a computing device for adjusting a region of interest (ROI) are provided. The method includes: receiving a image sequence including a current image and a previous image; generating a predefined searching area based on a previous ROI in the previous image; performing feature matching on multiple image features within the predefined searching area in the previous image and multiple image features within the predefined searching area in the current image; and adjusting a position of the previous ROI in the previous image based on the image features within the predefined searching area in the current image in response to that the image features within the predefined searching area in the current image satisfy a matching condition to obtain the current ROI in the current image.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: November 23, 2021
    Assignee: Wistron Corporation
    Inventors: Po-Chun Chen, Yu-Yen Chen, Kuo-Ting Huang
  • Patent number: 11140792
    Abstract: A display device including a display panel, an extension plate, and a spacing plate is provided. The display panel has a first substrate, a second substrate, and a flexible connecting unit. The second substrate is stacked on the first substrate and has an outer surface. The first substrate has a protruding portion extended out of the second substrate. The protruding portion has a protruding surface connected to the flexible connecting unit. The extension plate is stacked on the outer surface and has a portion extending out of the outer surface and being stacked on the protruding portion. A gap is formed between the extension plate and the flexible connecting unit. The spacing plate partially enters into the gap to be located between the flexible connecting unit and the extension plate.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 5, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Po-Chun Chen
  • Patent number: 11133320
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, in which a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner as the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: September 28, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kun-Hsin Chen, Hsuan-Tung Chu, Tsuo-Wen Lu, Po-Chun Chen
  • Patent number: 11088933
    Abstract: A system includes a provider network and a client network connected via a dedicated physical connection. The client network and the provider network exchange routing information using routing protocol messages, such as border gateway protocol (BGP) update messages exchanged during a BGP session. A provider network includes tag field values in outgoing routing protocol messages that indicate a portion of the provider network wherein resources of the provider network associated with a corresponding route are located. The client network may use the tag field value to determine whether to add the route to a routing table of the client network. A client network may also include tag field values in outgoing routing protocol messages to a provider network. The tag field values may indicate what portions of the provider network are to receive the routes from the client network. For example a tag field value may indicate that a route is to be propagated within a limited portion of the provider network.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: August 10, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Po-Chun Chen, Mark Edward Stalzer, Marco Eulenfeld
  • Patent number: 10984787
    Abstract: A multimedia apparatus includes a wireless transmission device, an audio receiving device, a processing device and a projection device. The audio receiving device is for receiving a first voice data. The processing device is coupled with the audio receiving device and the wireless transmission device. The processing device is for outputting the first voice data via the wireless transmission device. The projection device is coupled with the processing device. When the processing device receives a first image data corresponding to the first voice data via the wireless transmission device, the processing device operates the projection device to project a first projection picture according to the first image data. A multimedia system including the multimedia apparatus is also disclosed.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 20, 2021
    Assignee: PEGATRON CORPORATION
    Inventors: Po-Chun Chen, Tzu-Fang Huang, Chung-Kuan Wang, Chia-Ching Chen, Kuang-Hsun Hsieh, Chih-Hsien Tsung, Hsiang-Lin Yang, Tao-Hua Cheng, Cheng-Yu Kao, Nien-Chih Wang
  • Publication number: 20210075727
    Abstract: The following description is directed to configuring gateways in computer networks. For example, a method includes receiving a first request from a client associated with a configurable network. The first request can request associating a set of network addresses assigned to the configurable network to a gateway. A second request can be received from a client associated with the gateway. The second request can request accepting the association of the first request. It can be determined that the set of network addresses do not overlap with a network address space that is accessible using the gateway. Routing information can be generated for the gateway. The generated routing information can be used to configure the gateway for forwarding network packets between the client private network and the configurable network.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Applicant: Amazon Technologies, Inc.
    Inventors: Po-Chun Chen, Sanjay Arunkumar Bhal, James Michael Lamanna, Kim Thanh Do, Justin Thomas Smith
  • Patent number: 10903328
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: January 26, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Chia-Lung Chang, Yi-Wei Chen, Wei-Hsin Liu, Han-Yung Tsai
  • Patent number: 10848423
    Abstract: The following description is directed to configuring gateways in computer networks. For example, a method includes receiving a first request from a client associated with a configurable network. The first request can request associating a set of network addresses assigned to the configurable network to a gateway. A second request can be received from a client associated with the gateway. The second request can request accepting the association of the first request. It can be determined that the set of network addresses do not overlap with a network address space that is accessible using the gateway. Routing information can be generated for the gateway. The generated routing information can be used to configure the gateway for forwarding network packets between the client private network and the configurable network.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Po-Chun Chen, Sanjay Arunkumar Bhal, James Michael Lamanna, Kim Thanh Do, Justin Thomas Smith
  • Publication number: 20200349382
    Abstract: A method and a computing device for adjusting a region of interest (ROI) are provided. The method includes: receiving a image sequence including a current image and a previous image; generating a predefined searching area based on a previous ROI in the previous image; performing feature matching on multiple image features within the predefined searching area in the previous image and multiple image features within the predefined searching area in the current image; and adjusting a position of the previous ROI in the previous image based on the image features within the predefined searching area in the current image in response to that the image features within the predefined searching area in the current image satisfy a matching condition to obtain the current ROI in the current image.
    Type: Application
    Filed: August 7, 2019
    Publication date: November 5, 2020
    Applicant: Wistron Corporation
    Inventors: Po-Chun Chen, Yu-Yen Chen, Kuo-Ting Huang
  • Patent number: 10811272
    Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 20, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Ta-Wei Chiu, Chia-Lung Chang, Po-Chun Chen, Hong-Yi Fang, Yi-Wei Chen
  • Publication number: 20200326755
    Abstract: A shockproof element is applied to an electronic element. The shockproof element includes a first elastic portion, a second elastic portion and a connecting portion. The first elastic portion defines an opening. The second elastic portion is disposed corresponding to the first elastic portion. The second elastic portion includes a hollow column. The hollow column extends from the second elastic portion into the opening of the first elastic portion. The hollow column can fix the electronic element, and the first elastic portion and the second elastic portion jointly hold the electronic element. The connecting portion connects to the first elastic portion and the second elastic portion. An electronic device, which includes the shockproof element, the electronic element, a first housing and a second housing, is also provided.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Inventors: Chiao-Yi LIN, Po-Chun CHEN
  • Patent number: 10790289
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 29, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • Patent number: 10771309
    Abstract: A technology is described for updating an Autonomous System Number (ASN) in a Border Gateway Protocol (BGP) routing configuration. An example method may include receiving a request to update a BGP routing configuration on a gateway with an ASN associated with a customer. In response to the request, the BGP routing configuration on the gateway may be updated to replace a default ASN associated with a computing service provider with the ASN associated with the customer. The BGP routing configuration on the gateway may also be updated to allow the ASN associated with the customer to appear in an Autonomous System (AS) path at least twice, thereby allowing for BGP routes to be exchanged between gateways.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: September 8, 2020
    Inventors: Po-Chun Chen, Mark Edward Stalzer, Andrew Hemstreet Redmon
  • Publication number: 20200252375
    Abstract: A request to establish an encrypted VPN connection between a network external to a provider network connected to the provider network via a dedicated direct physical link and a set of resources of the provider network is received. A new isolated virtual network (IVN) is established to implement an encryption virtual private gateway to be used for the connection. One or more protocol processing engines (PPEs) are instantiated within the IVN, address information of the one or more PPEs is exchanged with the external network and a respective encrypted VPN tunnel is configured between each of the PPEs and the external network. Routing information pertaining to the set of resources is provided to the external network via at least one of the encrypted VPN tunnels, enabling routing of customer data to the set of resources within the provider network from the external network via an encrypted VPN tunnel implemented over a dedicated direct physical link between the external network and the provider network.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 6, 2020
    Applicant: Amazon Technologies, Inc.
    Inventors: Po-Chun Chen, Omer Hashmi, Sanjay Bhal
  • Patent number: 10735292
    Abstract: A physical interconnect having multiple virtual paths is coupled between network devices of independent networks operated by different entities. In one aspect, the interconnect is monitored so that the entities can simultaneously and separately monitor network traffic being exchanged across the interconnect. Each entity can be assigned two virtual paths through the interconnect to pass network traffic through their network device, over the interconnect, through a network device of the other entity, back over the interconnect link and back through their network device. The network devices can be configured to loop back network packets using a variety of loopback configurations. Hardware policers that monitor capacity usage of the virtual paths can also be tested.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Erik Klayton Klavon, Po-Chun Chen, James Michael Lamanna, Halley Jagarapu, Jagan Selvarajah
  • Publication number: 20200243541
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, in which a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner as the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 30, 2020
    Inventors: Kun-Hsin Chen, Hsuan-Tung Chu, Tsuo-Wen Lu, Po-Chun Chen