Patents by Inventor Po-Hao Tsai

Po-Hao Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804247
    Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10804254
    Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
  • Publication number: 20200312791
    Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • Publication number: 20200312773
    Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 1, 2020
    Inventors: Po-Hao TSAI, Meng-Liang LIN, Po-Yao CHUANG, Techi WONG, Shin-Puu JENG
  • Patent number: 10790162
    Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 10784123
    Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Publication number: 20200294983
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Publication number: 20200286843
    Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20200279836
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10763132
    Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Li-Hui Cheng, Po-Hao Tsai
  • Patent number: 10741520
    Abstract: A method of making a semiconductor device includes patterning a photoresist on a substrate to form a plurality of openings in the photoresist. A first opening is near a center of the substrate and has a first width. A second opening is near an edge of the substrate and has a second width smaller than the first width. A third opening is between the first opening and the second opening and has a third width greater than the second width and smaller than the first width. The method further includes plating a conductive material into each opening. Plating the conductive material includes plating the first conductive material in the first opening at a first current density; plating the first conductive material in the second opening at a second current density greater than the first current density; and plating the conductive material in the third opening at a third current density.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Publication number: 20200251456
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Li-Hsien Huang, Po-Hao Tsai, Ming-Shih Yeh, Ta-Wei Liu
  • Publication number: 20200243435
    Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Jing-Cheng Lin, Chi-Hsi Wu, Chen-Hua Yu, Po-Hao Tsai
  • Publication number: 20200243483
    Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tin-Hao Kuo, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Yu-Chia Lai, Po-Yuan Teng
  • Patent number: 10720403
    Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Publication number: 20200227264
    Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.
    Type: Application
    Filed: March 27, 2020
    Publication date: July 16, 2020
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Patent number: 10707135
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Hao Tseng, Chien-Ting Lin, Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Chueh-Fei Tai, Cheng-Ping Kuo
  • Publication number: 20200211962
    Abstract: A package structure and method for forming the same are provided. The package structure includes a die structure formed over a first interconnect structure, and the die structure includes a first region and a second region. The package structure includes a dam structure formed on the first region of the die structure, and a second interconnect structure formed over the die structure and the dam structure. The package structure also includes a package layer formed between the first interconnect structure and the second interconnect structure, and the package layer is formed on the second region of the die structure to surround the dam structure.
    Type: Application
    Filed: April 10, 2019
    Publication date: July 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hao TSAI, Techi WONG, Meng-Liang LIN, Yi-Wen WU, Po-Yao CHUANG, Shin-Puu JENG
  • Publication number: 20200211956
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die formed over an interconnect structure, an encapsulating layer formed over the interconnect structure to cover and surround the semiconductor die, and an interposer structure formed over the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure includes island layers arranged on the first surface of the insulating base and corresponding to the semiconductor die. A portion of the encapsulating layer is sandwiched by at least two of the island layers. Alternatively, the interposer structure includes a passivation layer covering the second surface of the insulating base and having a recess that is extended along a peripheral edge of the insulating base.
    Type: Application
    Filed: May 8, 2019
    Publication date: July 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Wen WU, Techi WONG, Po-Hao TSAI, Po-Yao CHUANG, Shih-Ting HUNG, Shin-Puu JENG
  • Publication number: 20200212537
    Abstract: A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.
    Type: Application
    Filed: September 3, 2019
    Publication date: July 2, 2020
    Inventors: Po-Yao Chuang, Po-Hao Tsai, Shin-Puu Jeng