Patents by Inventor Po-Hsin Lin

Po-Hsin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11120761
    Abstract: A driving substrate includes a substrate, at least one active device, a resistor, a first passivation layer and a second passivation layer. The active device including an oxide semiconductor layer and the resistor coupled to the active device are disposed on the substrate. The first passivation layer covers the active device, wherein a portion of the first passivation layer directly contacts to the oxide semiconductor layer such that the oxide semiconductor layer has a first conductivity. The second passivation layer covers the first passivation layer and the resistor, wherein a portion of the second passivation layer directly contacts to the resistor such that the resistor has a second conductivity. The first conductivity is different from the second conductivity.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 14, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20210272527
    Abstract: A trace structure of a display panel including a first metal layer and a second metal layer is provided. The first metal layer is configured to transmit a first voltage. The second metal layer is disposed under the first metal layer and configured to transmit a second voltage. The first metal layer and the second metal layer form the trace structure on the display panel, such that the trace structure has a capacitor structure. The trace structure is configured to connect a power input and a panel driver circuit.
    Type: Application
    Filed: March 2, 2021
    Publication date: September 2, 2021
    Applicant: E Ink Holdings Inc.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Po-Hsin Lin
  • Patent number: 10923068
    Abstract: A display device and a display driving circuit with electromagnetic interference suppression capability are provided. The display device includes a substrate, an active matrix, a display driver and a thin-film transistor (TFT) conditioning circuit. The active matrix disposed on the substrate includes multiple data lines, multiple gate lines and multiple pixels. The data lines intersect with the gate lines. The pixels are coupled to intersections of the data lines and the gate lines. The display driver disposed on the substrate generates signals for driving the data lines and/or the gate lines in response to a conditioned serial data clock. The TFT conditioning circuit disposed on the substrate is coupled to the display driver. The TFT conditioning circuit includes one or more TFTs, and attenuates an amplitude of a serial data clock in response to a predetermined gate bias to provide the conditioned serial data clock to the display driver.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 16, 2021
    Assignee: E INK HOLDINGS INC.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Yu-Lin Wang, Po-Hsin Lin
  • Patent number: 10672623
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 2, 2020
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20190362685
    Abstract: A display device and a display driving circuit with electromagnetic interference suppression capability are provided. The display device includes a substrate, an active matrix, a display driver and a thin-film transistor (TFT) conditioning circuit. The active matrix disposed on the substrate includes multiple data lines, multiple gate lines and multiple pixels. The data lines intersect with the gate lines. The pixels are coupled to intersections of the data lines and the gate lines. The display driver disposed on the substrate generates signals for driving the data lines and/or the gate lines in response to a conditioned serial data clock. The TFT conditioning circuit disposed on the substrate is coupled to the display driver. The TFT conditioning circuit includes one or more TFTs, and attenuates an amplitude of a serial data clock in response to a predetermined gate bias to provide the conditioned serial data clock to the display driver.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Applicant: E Ink Holdings Inc.
    Inventors: Xue-Hung TSAI, Wei-Tsung CHEN, Yu-Lin WANG, Po-Hsin LIN
  • Publication number: 20190122628
    Abstract: A driving substrate includes a substrate, at least one active device, a resistor, a first passivation layer and a second passivation layer. The active device including an oxide semiconductor layer and the resistor coupled to the active device are disposed on the substrate. The first passivation layer covers the active device, wherein a portion of the first passivation layer directly contacts to the oxide semiconductor layer such that the oxide semiconductor layer has a first conductivity. The second passivation layer covers the first passivation layer and the resistor, wherein a portion of the second passivation layer directly contacts to the resistor such that the resistor has a second conductivity. The first conductivity is different from the second conductivity.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 25, 2019
    Applicant: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20190115227
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: Wei-Tsung CHEN, Po-Hsin LIN, Xue-Hung TSAI
  • Patent number: 10193022
    Abstract: A pixel structure includes a substrate, a gate electrode disposed on the substrate, a capacitor electrode disposed on the substrate, a first insulation layer, an active layer disposed on the first insulation layer, a drain electrode, a source electrode and an extension electrode. The capacitor electrode is spaced apart from the gate electrode. The first insulation layer covers the gate electrode and the capacitor electrode. The first insulation layer has a recess vertically above the capacitor electrode. The drain and the source electrodes are disposed on the active layer and spaced apart from each other. The extension electrode extends from the drain electrode or the source electrode into the recess.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 29, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Henry Wang, Po-Hsin Lin
  • Patent number: 10186430
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: January 22, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20180323342
    Abstract: A pixel structure includes a substrate, a gate electrode disposed on the substrate, a capacitor electrode disposed on the substrate, a first insulation layer, an active layer disposed on the first insulation layer, a drain electrode, a source electrode and an extension electrode. The capacitor electrode is spaced apart from the gate electrode. The first insulation layer covers the gate electrode and the capacitor electrode. The first insulation layer has a recess vertically above the capacitor electrode. The drain and the source electrodes are disposed on the active layer and spaced apart from each other. The extension electrode extends from the drain electrode or the source electrode into the recess.
    Type: Application
    Filed: November 17, 2017
    Publication date: November 8, 2018
    Inventors: Xue-Hung TSAI, Wei-Tsung CHEN, Henry WANG, Po-Hsin LIN
  • Patent number: 10054810
    Abstract: A display apparatus includes at least one pixel structure, which includes an active device, an electric insulation layer and a pixel electrode. The electric insulation layer is disposed on the active device. The electric insulation layer has a trench and a via. The via is located on a bottom surface of the trench. A portion of the electric insulation layer surrounding the trench is monolithically connected to another portion of the electric insulation layer surrounding the via. A pixel electrode has a first electrode portion and a second electrode portion connected to each other. The first electrode portion is located in the trench. A thickness of the first electrode portion is less than a depth of the trench. The second electrode portion is located in the via and is electrically connected to the active device through the via.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: August 21, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Henry Wang, Po-Hsin Lin
  • Patent number: 10026355
    Abstract: A display device includes a substrate and a peripheral circuit structure on the substrate. The peripheral circuit includes a common electrode layer between the ESD protection diode and a pixel unit of the substrate, an ESD protection diode, an isolation layer covering the common electrode layer, a first conductive line on the isolation layer and over the common electrode layer, and a second conductive line on the isolation layer and over the common electrode layer. Two ends of the first conductive line are respectively electrically connected to the ESD protection diode and the pixel unit. Two ends of the second conductive line are electrically connected to the first conductive line on positions that are between the ESD protection diode and the common electrode layer and between the pixel unit and the common electrode layer to respectively form a first junction and a second junction.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: July 17, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Henry Wang, Po-Hsin Lin
  • Publication number: 20180088397
    Abstract: A display apparatus includes at least one pixel structure, which includes an active device, an electric insulation layer and a pixel electrode. The electric insulation layer is disposed on the active device. The electric insulation layer has a trench and a via. The via is located on a bottom surface of the trench. A portion of the electric insulation layer surrounding the trench is monolithically connected to another portion of the electric insulation layer surrounding the via. A pixel electrode has a first electrode portion and a second electrode portion connected to each other. The first electrode portion is located in the trench. A thickness of the first electrode portion is less than a depth of the trench. The second electrode portion is located in the via and is electrically connected to the active device through the via.
    Type: Application
    Filed: July 6, 2017
    Publication date: March 29, 2018
    Inventors: Xue-Hung TSAI, Wei-Tsung CHEN, Henry WANG, Po-Hsin LIN
  • Publication number: 20180047587
    Abstract: A method of manufacturing a transistor, includes: (i) forming a metal-oxide semiconductor layer over a substrate; (ii) forming a source electrode and a drain electrode on different sides of the metal-oxide semiconductor layer; (iii) forming a dielectric layer over the source electrode, the drain electrode, and the metal-oxide semiconductor layer; (iv) forming a hydrogen-containing insulating layer over the dielectric layer, in which the hydrogen-containing insulating layer has an aperture exposing a surface of the dielectric layer, and the aperture is overlapped with the metal-oxide semiconductor layer when viewed in a direction perpendicular to the surface; (v) increasing a hydrogen concentration of a portion of the metal-oxide semiconductor layer by treating the hydrogen-containing insulating layer so to form a source region and a drain region; and (vi) forming a gate electrode in the aperture.
    Type: Application
    Filed: May 12, 2017
    Publication date: February 15, 2018
    Inventors: Wei-Tsung CHEN, Po-Hsin LIN, Xue-Hung TSAI
  • Patent number: 9653530
    Abstract: An OLED module equipped with vertical electric connection structure includes a substrate, a plurality of OLED clusters, an anode wire structure and a cathode wire structure. The substrate is extended toward a first direction. The OLED clusters are located on the substrate in the first direction. The anode wire structure includes a bottom layer wire set, an insulation layer, a middle wire layer set and a top layer wire set. The bottom layer wire set is located on the substrate. The insulation layer is located on the bottom layer wire set. The top layer wire set is located on the insulation layer. The cathode wire structure is located on the substrate and extended axially thereof. The middle layer wire set runs through the insulation layer and forms vertical connection between the bottom layer wire set and the top layer wire set.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: May 16, 2017
    Assignee: WiseChip Semiconductor Inc.
    Inventors: Po-Hsin Lin, Shih-Hung Chang, Shang-Chih Lin, Chia-Chi Huang, I-Hsuan Lin, Sheng-Hsu Shih, Chien-Hsun Chen, Yung-Cheng Tsai, Chien-Le Li
  • Patent number: 9622366
    Abstract: A display panel having a wireless charging function is provided, and the display panel includes a first substrate, an induction coil layer, a display pixel layer, and a second substrate. The induction coil layer is disposed on the first substrate. The induction coil layer includes at least one induction coil. The induction coil layer is adapted for collaborating with a wireless charging power supply, such that the induction coil layer executes the wireless charging function. The display pixel layer is disposed on the induction coil layer. The second substrate is disposed on the display pixel layer.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 11, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Chin-Wen Lin, Po-Hsin Lin, Chi-Liang Wu, Ted-Hong Shinn
  • Publication number: 20160260793
    Abstract: An OLED module equipped with vertical electric connection structure includes a substrate, a plurality of OLED clusters, an anode wire structure and a cathode wire structure. The substrate is extended toward a first direction. The OLED clusters are located on the substrate in the first direction. The anode wire structure includes a bottom layer wire set, an insulation layer, a middle wire layer set and a top layer wire set. The bottom layer wire set is located on the substrate. The insulation layer is located on the bottom layer wire set. The top layer wire set is located on the insulation layer. The cathode wire structure is located on the substrate and extended axially thereof The middle layer wire set runs through the insulation layer and forms vertical connection between the bottom layer wire set and the top layer wire set.
    Type: Application
    Filed: February 3, 2016
    Publication date: September 8, 2016
    Inventors: Po-Hsin LIN, Shih-Hung CHANG, Shang-Chih LIN, Chia-Chi HUANG, I-Hsuan LIN, Sheng-Hsu SHIH, Chien-Hsun CHEN, Yung-Cheng TSAI, Chien-Le LI
  • Patent number: 9275569
    Abstract: A threshold voltage sensing circuit applied in a display panel includes a first sensor and a second sensor. The first sensor positioned in the display panel receives an operation signal at a regular time point after start-up and continuously receives multiple driving signals which are the same as those received by the pixel circuits of the display panel and outputs a first output voltage accordingly. The second sensor positioned in the display panel receives the driving signals at a regular time point after start-up and outputs a second output voltage accordingly. When the voltage difference between the first output voltage and the second output voltage is beyond a variation standard, the low level of the gate voltage of the pixel circuit is adjusted.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: March 1, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Chi-Liang Wu, Po-Hsin Lin, Young-Ran Chuang, Chin-Wen Lin, Ted-Hong Shinn
  • Publication number: 20150364499
    Abstract: A substrate structure including a flexible substrate, a gate line, a gate, an inorganic insulation layer, a semiconductor layer, a source, a drain, an inorganic passivation layer and an organic insulation layer is provided. The gate is electrically connected to the gate line. The inorganic insulation layer covers the gate and exposes a portion of the flexible substrate. The semiconductor layer is disposed on the inorganic insulation layer and disposed corresponding to the gate. The source and the drain extend from the inorganic insulation layer to the semiconductor layer and expose a portion of the semiconductor layer. The inorganic passivation layer covers portions of the source and the drain and directly contacts to the semiconductor layer exposed by the source and the drain. The organic insulation layer covers the source, the drain, the inorganic passivation layer and the flexible substrate exposed by the inorganic insulation layer.
    Type: Application
    Filed: March 24, 2015
    Publication date: December 17, 2015
    Inventors: Kuan-Yi Lin, Po-Hsin Lin, Fang-An Shu, Cheng-Hang Hsu, Tzung-Wei Yu
  • Patent number: 9177498
    Abstract: A display panel includes a gate driving circuit and a control circuit. The gate driving circuit includes a plurality of circuit stages. An Nth-circuit stage of the circuit stages includes a start unit, a drive unit, a first pull-down unit, a second pull-down unit, and a current detecting unit. The drive unit is configured to provide a dock signal to an Nth-output terminal. The first pull-down unit is configured to make an enable node have a first pull-down voltage. The second pull-down unit is configured to provide a disable node with a second pull-down voltage. The current detecting unit is configured to detect an error current passing through the first pull-down unit and output an error signal according to the error current. The control circuit is configured to adjust the second pull-down voltage according to the error signal of the Nth-circuit stage.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: November 3, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Chi-Liang Wu, Po-Hsin Lin, Chin-Wen Lin, Ted-Hong Shinn