Patents by Inventor Po-Hsun Chen

Po-Hsun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929767
    Abstract: A transmission interface between at least a first module and a second module is proposed. The transmission interface includes at least two physical transmission mediums. Each physical transmission medium is arranged to carry a multiplexed signal in which at least two signals are integrated. The at least two physical transmission mediums include a first physical transmission medium arranged to carry a first multiplexed signal including a first IF signal and a reference clock signal. The first IF signal and the reference clock signal are at different frequencies.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 12, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chieh-Hsun Hsiao, Ming-Chou Wu, Wen-Chang Lee, Narayanan Baskaran, Wei-Hsin Tseng, Jenwei Ko, Po-Sen Tseng, Hsin-Hung Chen, Chih-Yuan Lin, Caiyi Wang
  • Publication number: 20220277933
    Abstract: A wafer treatment system is provided. The wafer treatment system includes a wafer treatment chamber defining a treatment area within which a wafer is treated. The wafer treatment system includes a gas injection system. The gas injection system includes a gas injector configured to inject a first gas, used for treatment of the wafer, into the treatment area. A first gas tube is configured to conduct the first gas at a first temperature to the gas injector. The gas injection system includes a heating enclosure enclosing the gas injector. A second gas tube is configured to conduct a heated gas to the heating enclosure to increase an enclosure temperature at the heating enclosure to a second enclosure temperature. A temperature of the first gas is increased in the gas injector from the first temperature to a second temperature due to the second enclosure temperature at the heating enclosure.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Po Hsun CHEN, Chun Wei CHOU, Keng-Ying LIAO, Tzu-Pin LIN, Tai Chin WU, Su-Yu YEH, Po-Zen CHEN
  • Patent number: 11333924
    Abstract: A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated with backlight illumination from a direct-lit backlight unit. The backlight unit may include an array of light-emitting diodes on a printed circuit board. The backlight unit may include first, second, and third light spreading layers formed over the array of light-emitting diodes. A color conversion layer may be formed over the first, second, and third light spreading layers. First and second brightness enhancement films may be formed over the color conversion layer.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: May 17, 2022
    Assignee: Apple Inc.
    Inventors: Wei Lv, Pee Khiam So, Wenyong Zhu, Daming Xu, Victor H. Yin, Mookyung Son, Ryan A. Zimmerman, Ziruo Hong, Rong Liu, Jun Qi, Po Hsun Chen, Zhenbin Ge, Fei Yan, Wei He
  • Patent number: 11289592
    Abstract: A structure to increase the breakdown voltage of the high electron mobility transistor is provided to solve the problem of function loss under a high voltage state. The structure includes a substrate, a conducting layer located on the substrate, a gate insulating layer and an electric-field-dispersion layer. The upper portion of the conducting layer is an electron supply layer, and the lower portion of the conducting layer is an electron tunnel layer. The gate insulating layer is laminated on the electron supply layer. The electric-field-dispersion layer is laminated on the gate insulating layer. The dielectric constant of the electric-field-dispersion layer is smaller than that of the gate insulating layer. A gate electrode is located between the electric-field-dispersion layer and the gate insulating layer. A source and a drain electrodes are respectively electrically connected to the electric-field-dispersion layer, the gate insulating layer, the electron supply layer, and the electron tunnel layer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: March 29, 2022
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Yu-Ching Tsao, Yu-Lin Tsai, Po-Hsun Chen, Yu-Shan Lin, Wen-Chung Chen
  • Publication number: 20220082523
    Abstract: A gas sensor and a method for manufacturing the gas sensor are disclosed. The gas sensor includes a substrate, a heating member disposed on the substrate, a sensing layer covering the heating member, and two electrodes respectively electrically connected to the sensing layer. The sensing layer includes a doping element with an electronegativity greater than 2. The method for manufacturing the gas sensor includes a deposition process stacking a heating member, a sensing layer, and two electrodes on a substrate by deposition, and a doping process introducing a doping gas when depositing the sensing layer.
    Type: Application
    Filed: November 4, 2020
    Publication date: March 17, 2022
    Inventors: Ting-Chang Chang, Yi-Ting Tseng, Chun-Chu Lin, Wen-Chung Chen, Po-Hsun Chen, Shih-Kai Lin
  • Publication number: 20220069208
    Abstract: A resistive random access memory and an initialization method thereof are disclosed. The initialization method includes irradiating a memory device with an electromagnetic wave and manipulating a switching voltage to switch the memory device between a high resistance state and a low resistance state. The electromagnetic wave has a frequency of above 1016 Hertz. The resistive random access memory includes a plurality of memory devices and a switching circuit respectively electrically connected to the plurality of memory devices. Each of the plurality of memory devices has a resistance-changing layer and two electrode layers respectively located on an upper surface and a lower surface of the resistance-changing layer.
    Type: Application
    Filed: November 4, 2020
    Publication date: March 3, 2022
    Inventors: Ting-Chang Chang, Yi-Ting Tseng, Chun-Chu Lin, Wen-Chung Chen, Shih-Kai Lin, Po-Hsun Chen
  • Publication number: 20220037531
    Abstract: A thin film transistor is used to solve a problem of low process efficiency of the conventional thin film transistor in preventing hydrogen diffusion. The thin film transistor includes a substrate, multilayer thin films laminated on the substrate, and at least one fluorine-containing thin film laminated in substitution for the multilayer thin films. Each of the multilayer thin films is a gate insulating layer, an active layer, a buffer layer, and a dielectric layer or a protective layer. Each of the at least one fluorine-containing thin film is a fluorine-doped insulating layer, a fluorine-doped active layer, a fluorine-doped buffer layer, and a fluorine-doped dielectric layer or a fluorine-doped protective layer. The invention further discloses a method for manufacturing the thin film transistor.
    Type: Application
    Filed: September 11, 2020
    Publication date: February 3, 2022
    Inventors: Ting-Chang Chang, Yu-Lin Tsai, Yu-Ching Tsao, Hong-Chih Chen, Shin-Ping Huang, Mao-Chou Tai, Po-Hsun Chen
  • Publication number: 20210367068
    Abstract: A structure to increase the breakdown voltage of the high electron mobility transistor is provided to solve the problem of function loss under a high voltage state. The structure includes a substrate, a conducting layer located on the substrate, a gate insulating layer and an electric-field-dispersion layer. The upper portion of the conducting layer is an electron supply layer, and the lower portion of the conducting layer is an electron tunnel layer. The gate insulating layer is laminated on the electron supply layer. The electric-field-dispersion layer is laminated on the gate insulating layer. The dielectric constant of the electric-field-dispersion layer is smaller than that of the gate insulating layer. A gate electrode is located between the electric-field-dispersion layer and the gate insulating layer. A source and a drain electrodes are respectively electrically connected to the electric-field-dispersion layer, the gate insulating layer, the electron supply layer, and the electron tunnel layer.
    Type: Application
    Filed: June 19, 2020
    Publication date: November 25, 2021
    Inventors: Ting-Chang Chang, Yu-Ching Tsao, Yu-Lin Tsai, Po-Hsun Chen, Yu-Shan Lin, Wen-Chung Chen
  • Patent number: 9935265
    Abstract: A resistive random access memory overcomes the low reliability of the conventional resistive random access memory. The resistive random access memory includes a resistance changing layer and two electrode layers. The two electrode layers are coupled with the resistance changing layer. Each of the two electrode layers includes a doping area containing a heavy element. In such an arrangement, the above deficiency can be overcome.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: April 3, 2018
    Assignee: National Sun Yat-Sen University
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan, Po-Hsun Chen
  • Patent number: 9925530
    Abstract: The present invention relates to a nanoporous thin film and a method for fabricating the same. The nanoporous thin film fabricating method for fabricating a nanoporous thin film with a composite photocatalyst structure for a photodegradation and a water purification includes providing a porous substrate with a plurality of through-nanopores therein, each of which through-nanopores have an inner tube wall; forming an oxide-based photocatalyst layer over the porous substrate and the inner tube wall by using a first chemical-based deposition process; and forming a metal-based photocatalyst layer on a part of the oxide-based photocatalyst layer by using a second chemical-based deposition process.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: March 27, 2018
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tsong-Pyng Perng, Hsueh-Shih Chen, Chung-Yi Su, Po-Hsun Chen
  • Publication number: 20170346004
    Abstract: A resistive random access memory overcomes the low reliability of the conventional resistive random access memory. The resistive random access memory includes a resistance changing layer and two electrode layers. The two electrode layers are coupled with the resistance changing layer. Each of the two electrode layers includes a doping area containing a heavy element. In such an arrangement, the above deficiency can be overcome.
    Type: Application
    Filed: October 12, 2016
    Publication date: November 30, 2017
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan, Po-Hsun Chen
  • Publication number: 20160067697
    Abstract: The present invention relates to a nanoporous thin film and a method for fabricating the same. The nanoporous thin film fabricating method for fabricating a nanoporous thin film with a composite photocatalyst structure for a photodegradation and a water purification includes providing a porous substrate with a plurality of through-nanopores therein, each of which through-nanopores have an inner tube wall; forming an oxide-based photocatalyst layer over the porous substrate and the inner tube wall by using a first chemical-based deposition process; and forming a metal-based photocatalyst layer on a part of the oxide-based photocatalyst layer by using a second chemical-based deposition process.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 10, 2016
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Tsong-Pyng Perng, Hsueh-Shih Chen, Chung-Yi Su, Po-Hsun Chen
  • Patent number: 8940244
    Abstract: The present invention relates to hierarchical structured nanotubes, to a method for preparing the same and to an application for the same, wherein the nanotubes include a plurality of connecting nanotubes for constituting a three-dimensional multi-dendrite morphology; and the method includes the following steps: (A) providing a polymer template including a plurality of organic nanowires; (B) forming an inorganic layer on the surface of the organic nanowires in the polymer template; and (C) performing a heat treatment on the polymer template having the inorganic layer on the surface so that partial atoms of the organic nanowires enter the inorganic layer.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 27, 2015
    Assignee: National Tsing Hua University
    Inventors: Hsueh-Shih Chen, Po-Hsun Chen, Jeng Liang Kuo, Tsong-Pyng Perng
  • Publication number: 20070258952
    Abstract: The present invention includes compositions and methods for the knockdown of one or more genes to a target cell in need of gene therapy by using an siRNA transgene that is integrated into a replication-competent, oncolytic adenovirus.
    Type: Application
    Filed: May 4, 2007
    Publication date: November 8, 2007
    Applicants: BAYLOR RESEARCH INSTITUTE, MUREX PHARMACEUTICALS, BAYLOR UNIVERSITY
    Inventors: Alex W. Tong, Yu An Zhang, John J. Nemunaitis, Yuqiao Shen, Po-hsun Chen, Shirley K. Samuel
  • Patent number: 7088592
    Abstract: An electronic device utilizing an electrostatic discharge (ESD) protection structure. The electronic device comprises a housing and a printed circuit board (PCB) with an ESD protection structure disposed thereon. The PCB has at least one metal layer with a ground circuit and a functional circuit. The ground circuit includes at least one device-protecting area near the edge of the PCB and exposed on the surface thereof. The device-protecting area is covered by a thick conductive layer, and electric components are disposed nearby, such that static electricity can be transferred to ground through the ground circuit of the PCB to protect the electronic device from interferences and damages.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: August 8, 2006
    Assignee: ASUSTek Computer Inc.
    Inventors: Po-Chang Su, Po-Hsun Chen
  • Publication number: 20060039999
    Abstract: A pharmaceutical composition for inhibition of tumor growth or metastasis which comprises an effective amount of Phyllanthus urinaria L. extracts, or the combination of the foregoing Phyllanthus urinaria L. extracts and pharmaceutical acceptable carries, adjuvants or excipients.
    Type: Application
    Filed: June 21, 2005
    Publication date: February 23, 2006
    Applicant: Hepaguard Biotechnology (Int'l) Co., Ltd.
    Inventors: Jui Lin, Wendy Mach, Po-Hsun Chen
  • Publication number: 20050088832
    Abstract: An electronic device utilizing an electrostatic discharge (ESD) protection structure. The electronic device comprises a housing and a printed circuit board (PCB) with an ESD protection structure disposed thereon. The PCB has at least one metal layer with a ground circuit and a functional circuit. The ground circuit includes at least one device-protecting area near the edge of the PCB and exposed on the surface thereof. The device-protecting area is covered by a thick conductive layer, and electric components are disposed nearby, such that static electricity can be transferred to ground through the ground circuit of the PCB to protect the electronic device from interferences and damages.
    Type: Application
    Filed: August 19, 2004
    Publication date: April 28, 2005
    Inventors: Po-Chang Su, Po-Hsun Chen