Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: A power heat dissipation device includes a heat-conducting layer, a heat sink and at least one cooling chip. The heat-conducting layer has a heat-absorbing surface and a heat-dissipating surface. The heat sink is in thermal contact with the heat-dissipating surface, and a heat-conducting section is formed in the heat sink. The cooling chip is embedded in the heat sink and disposed adjacent to the heat transferring channel. The cooling chip has a cooling surface which is perpendicular to the heat-absorbing surface. The cooling surface faces the heat transferring channel. The cooling chip removes heat from the heat-conducting section in the heat sink.

Abstract: A power heat dissipation device includes a heat-conducting layer, a heat sink and at least one cooling chip. The heat-conducting layer has a heat-absorbing surface and a heat-dissipating surface. The heat sink is in thermal contact with the heat-dissipating surface, and a heat-conducting section is formed in the heat sink. The cooling chip is embedded in the heat sink and disposed adjacent to the heat transferring channel. The cooling chip has a cooling surface which is perpendicular to the heat-absorbing surface. The cooling surface faces the heat transferring channel. The cooling chip removes heat from the heat-conducting section in the heat sink.

Abstract: A power heat dissipation device includes a heat-conducting layer, a heat sink and at least one thermoelectric cooling chip. The heat-conducting layer has a heat-absorbing-surface and a heat-dissipating-surface which are opposite to each other. The heat sink is in thermal contact with the heat-dissipating-surface of the heat-conducting layer. The at least one thermoelectric cooling chip is embedded in the heat-conducting layer. The heat-conducting layer has an effective heat-conducting-region. A1 is the area on the heat-absorbing-surface which the effective heat-conducting-region projects on, and A2 is the area on the heat-absorbing-surface which the thermoelectric cooling chip projects on. The ratio of A2 to A1 is between 0.15 and 0.58.

Abstract: A motor controller and a cooling method thereof are provided. The motor controller includes: a first power module; a second power module; a first heat sink having first fins; a second heat sink having second fins; a first partition board; a second partition board; a housing disposed at external sides of the first and second partition boards, with a first channel formed between the housing and the first partition board; a conduit connected to a rear end of the first heat sink and extending to an outlet of the housing; a first flow channel; and a second flow channel passing through the first channel and the gaps of the second fins, for second cold air to be introduced, and processed by a heat exchange process performed by the second power module to generate second hot air that is expelled to the outlet of the housing through the second flow channel.

Abstract: A method and apparatus for handling branch instructions contained within a source program includes applying a set of heuristics to classify each of the branch instructions in the source program as either a hard-to-predict type or a simple type of branch. A system implements a multi-heuristic branch predictor comprising a large, relatively simple branch predictor having many entries, to accommodate the majority of branch instructions encountered in a program, and a second, relatively small, sophisticated branch predictor having a few entries. The sophisticated branch predictor predicts the target addresses of the hard-to-predict branches. By mapping hard-to-predict branches to the sophisticated branch predictor, and easy-to-predict branches to the relatively simple branch predictor, overall performance is enhanced.

Abstract: A method and apparatus for handling branch instructions contained within a source program includes applying a set of heuristics to classify each of the branch instructions in the source program as either a hard-to-predict type or a simple type of branch. A system implements a multi-heuristic branch predictor comprising a large, relatively simple branch predictor having many entries, to accommodate the majority of branch instructions encountered in a program, and a second, relatively small, sophisticated branch predictor having a few entries. The sophisticated branch predictor predicts the target addresses of the hard-to-predict branches. By mapping hard-to-predict branches to the sophisticated branch predictor, and easy-to-predict branches to the relatively simple branch predictor, overall performance is enhanced.

Abstract: A method, performed by a computer, for optimizing a computer program having a plurality of instructions that form a loop. The loop has a first block and a second block. The first block has at least one instruction for using a variable and the second block has an ambiguous definition instruction for defining the variable. A load instruction for loading the variable into a register is inserted prior to the plurality of instructions that form the loop. In addition, at least one instruction for using the variable is replaced with an instruction for using the register. Further, a load instruction for loading the variable into the register is inserted after the ambiguous definition instruction.

Abstract: A method of facilitating optimization of computer program code. The code includes instructions for performing a plurality of loops, with each loop including at least one memory reference. The program code is instrumented to cause a memory reference trace to be generated when the program code is executed. The loops in the program code are identified from the trace. For each loop, a plurality of performance parameters relating to the memory references contained within the loop, including dynamic memory usage information and cache statistics, are computed based on the information in the trace. The performance parameters are then applied to a plurality of sets of conditions. Each set of conditions corresponds to one of a plurality of known optimization techniques to determine whether each set of conditions is satisfied for each loop. The optimization techniques include loop transformations and data restructuring techniques.

Abstract: In a computer program, a branch instruction selects a prediction heuristic from a plurality of prediction heuristics for predicting whether the branch will be taken during execution of the program by a computer. A current pattern comprises a number of consecutive identical branch decisions for the instruction. A prior pattern comprises a number of consecutive identical prior branch decisions for the instruction, the prior branch decisions occurring prior to the branch decisions comprised by the current pattern. The selected prediction heuristic generates a branch prediction using the current pattern and the prior pattern. The selected prediction heuristic is identified by adding profiling instructions to the program to compute history information for the branch instruction. The profiling instructions input the branch history information to a plurality of prediction heuristics, and each prediction heuristic outputs a prediction of whether the branch instruction will be taken.