Patents by Inventor Po-Hung Chen
Po-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8802327Abstract: The present invention discloses an electrode structure capable of separately delivering gas and fluid which is applied to a passive fuel cell. The electrode structure includes an electrode portion and a water removal plate, and the electrode portion is adjacent to the water removal plate. The water removal plate includes a first surface, a second surface opposite to the first surface, a plurality of gas passages passing from the first surface to the second surface, and a plurality of liquid passages disposed on the first surface. The surfaces of the gas passages are treated with hydrophobic treatment, and the surfaces of the liquid passages are treated with hydrophilic treatment.Type: GrantFiled: March 8, 2011Date of Patent: August 12, 2014Assignee: National Tsing Hua UniversityInventors: Fan Gang Tseng, Hsien Chih Peng, Po Hung Chen
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Publication number: 20140118983Abstract: An assembling structure includes a ground wire, an inverter, a first fixing element, and a clamping device. The inverter includes a casing. The clamping device is disposed on the casing. The clamping device includes a first end, a second end, and a pressing part between the first end and the second end. The second end of the clamping device is previously fixed on the casing. After the ground wire is transferred through an entrance between the first end of the clamping device and the casing, the ground wire is clamped between the pressing part and the casing. Afterwards, by using the fixing element, the first end of the clamping device is fixed on the casing, the ground wire is fixed on the casing by the pressing part of the clamping device, and the inverter is fixed on the rack simultaneously.Type: ApplicationFiled: March 7, 2013Publication date: May 1, 2014Applicant: DELTA ELECTRONICS, INC.Inventors: Sheng-Hua Li, Po-Hung Chen
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Patent number: 8646950Abstract: A display apparatus includes a panel module and a backlight module. The backlight module is disposed under the panel module. The backlight module includes a frame, a light guide plate, and a reflector. The frame supports the edge of the light guide plate. The reflector is disposed at the bottom of the light guide plate. The edge of the reflector and the edge of the frame horizontally form an engaging seam without overlapping, and the engaging seam is substantially in a serrated shape.Type: GrantFiled: October 23, 2012Date of Patent: February 11, 2014Assignee: AU Optronics CorporationInventors: Yi-Fan Lin, Shih-Yao Lin, Chieh-Jen Cheng, Po-Hung Chen
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Patent number: 8489814Abstract: A cache controller, a method for controlling the cache controller, and a computing system comprising the same are provided. The computer system comprises a processor and a cache controller. The cache controller is electrically connected to the processor and comprises a first port, a second port, and at least one cache. The first port is configured to receive an address of a content, wherein a type of the content is one of instruction and data. The second port is configured to receive an information bit corresponding to the content, wherein the information bit indicates the type of the content. The at least one cache comprises at least one cache lines. Each of the cache lines comprises a content field and corresponding to an information field. The content and the information bit is stored in the content field of one of the cache lines and the corresponding information field respectively according to the information bit and the address. Thereby, instruction and data are separated in a unified cache.Type: GrantFiled: June 23, 2009Date of Patent: July 16, 2013Assignee: Mediatek, Inc.Inventors: Po-Hung Chen, Chang-Hsien Tai
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Patent number: 8466732Abstract: An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.Type: GrantFiled: October 8, 2010Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hung Chen, Kuoyuan (Peter) Hsu, David Yen, Sung-Chieh Lin
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Publication number: 20130107571Abstract: A display apparatus includes a panel module and a backlight module. The backlight module is disposed under the panel module. The backlight module includes a frame, a light guide plate, and a reflector. The frame supports the edge of the light guide plate. The reflector is disposed at the bottom of the light guide plate. The edge of the reflector and the edge of the frame horizontally form an engaging seam without overlapping, and the engaging seam is substantially in a serrated shape.Type: ApplicationFiled: October 23, 2012Publication date: May 2, 2013Applicant: AU Optronics CorporationInventors: Yi-Fan LIN, Shih-Yao Lin, Chieh-Jen Cheng, Po-Hung Chen
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Patent number: 8432759Abstract: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.Type: GrantFiled: June 28, 2010Date of Patent: April 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuoyuan Hsu, Po-Hung Chen, Jiann-Tseng Huang, Subramani Kengeri
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Patent number: 8427857Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.Type: GrantFiled: May 6, 2010Date of Patent: April 23, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Hung Chen, Sung-Chieh Lin, Kuoyuan Hsu, Jiann-Tseng Huang
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Publication number: 20130097340Abstract: A USB multi-functions device and a method thereof. The USB multi-functions device is capable of supporting a plurality of functions for a USB host, has a first software module installed to support a first selection of the functions, and comprises a function switch, a memory, and a controller. The function switch receives an input signal unrelated to any previous signal to switch from the first to a second selection of functions. The memory comprises a switch program executable by a controller, the first software module supporting the first selection of the functions and a second software module supporting the second selection of the functions. The controller executes the switch program to determine the second selection of the functions based on the input signal, and installs the second software module.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Applicant: MEDIATEK INC.Inventor: Po-Hung Chen
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Publication number: 20120212212Abstract: In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.Type: ApplicationFiled: February 14, 2012Publication date: August 23, 2012Inventors: Po-Hung CHEN, Makoto TAKAMIYA, Takayasu SAKURAI
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Patent number: 8194490Abstract: Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.Type: GrantFiled: September 8, 2010Date of Patent: June 5, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hung Chen, Chin-Huang Wang, Yen-Chieh Huang, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
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Publication number: 20120086495Abstract: An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.Type: ApplicationFiled: October 8, 2010Publication date: April 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Hung CHEN, Kuoyuan (Peter) HSU, David YEN, Sung-Chieh LIN
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Publication number: 20120081165Abstract: A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jiann-Tseng HUANG, Sung-Chieh LIN, Kuoyuan HSU, Po-Hung CHEN
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Publication number: 20120073284Abstract: A hot zone heat transfer structure of a Stirling engine is provided. One end of a cylinder includes a heated head, with its end wall connected with a hot air pipe. The cylinder accommodates a piston. The piston has an end surface corresponding to the end wall, between which a hot zone is defined. The end wall is fitted with a protruding heat conductor towards the piston, and the end surface is fitted with a concave heat-conducting portion, enabling normal overlapping of the ends of both the heat conductor and the heat-conducting portion. The overlapping may vary with the changing locations of the piston. A flanged section is set externally onto said heat conductor towards the exterior of the end wall. The heat from the head can be transferred to the central area of the hot zone via the help of the heat conductor and heat-conducting portion.Type: ApplicationFiled: March 15, 2011Publication date: March 29, 2012Applicant: MARKETECH INTERNATIONAL CORP.Inventors: Tien-Ting CHEN, Chung-Ping Liu, Yin-Nan Huang, Po-Hung Chen, Yu-Ling Huang, Han-Hsun Yang, Ching-Hsiang Cheng
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Publication number: 20120057423Abstract: Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.Type: ApplicationFiled: September 8, 2010Publication date: March 8, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Hung CHEN, Chin-Huang WANG, Yen-Chieh HUANG, Sung-Chieh LIN, Kuoyuan (Peter) HSU
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Publication number: 20110273949Abstract: A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.Type: ApplicationFiled: May 6, 2010Publication date: November 10, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hung CHEN, Sung-Chieh LIN, Kuoyuan HSU, Jiann-Tseng HUANG
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Publication number: 20110223503Abstract: The present invention discloses an electrode structure capable of separately delivering gas and fluid which is applied to a passive fuel cell. The electrode structure includes an electrode portion and a water removal plate, and the electrode portion is adjacent to the water removal plate. The water removal plate includes a first surface, a second surface opposite to the first surface, a plurality of gas passages passing from the first surface to the second surface, and a plurality of liquor passages disposed on the first surface. The surfaces of the gas passages are treated with hydrophobic treatment, and the surfaces of the liquor passages are treated with hydrophilic treatment.Type: ApplicationFiled: March 8, 2011Publication date: September 15, 2011Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Fan Gang Tseng, Hsien Chih Peng, Po Hung Chen
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Patent number: 7961270Abstract: A display device and a manufacturing method thereof are provided. The display device includes a light guide, a light source, and a brightness enhancement film (BEF), and a dual brightness enhancement film (DBEF). The light guide has a first edge along a first direction and a second edge adjacent to the first edge corresponding to the light source. The BEF is disposed on the light guide and has a plurality of prisms along a second direction which rotates from 0 to 90 degrees with respect to the first direction. The DBEF has a transmission axis along a third direction which also rotates from 0 to 90 degrees with respect to the first direction.Type: GrantFiled: August 20, 2009Date of Patent: June 14, 2011Assignee: AU Optronics CorporationInventors: Kuang-Hua Mei, Shih-Ping Lin, Po-Hung Chen
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Publication number: 20100329055Abstract: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.Type: ApplicationFiled: June 28, 2010Publication date: December 30, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuoyuan HSU, Po-Hung CHEN, Jiann-Tseng HUANG, Subramani KENGERI
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Publication number: 20100325364Abstract: A cache controller, a method for controlling the cache controller, and a computing system comprising the same are provided. The computer system comprises a processor and a cache controller. The cache controller is electrically connected to the processor and comprises a first port, a second port, and at least one cache. The first port is configured to receive an address of a content, wherein a type of the content is one of instruction and data. The second port is configured to receive an information bit corresponding to the content, wherein the information bit indicates the type of the content. The at least one cache comprises at least one cache lines. Each of the cache lines comprises a content field and corresponding to an information field. The content and the information bit is stored in the content field of one of the cache lines and the corresponding information field respectively according to the information bit and the address. Thereby, instruction and data are separated in a unified cache.Type: ApplicationFiled: June 23, 2009Publication date: December 23, 2010Applicant: MEDIATEK INC.Inventors: Po-Hung CHEN, Chang-Hsien TAI