Patents by Inventor Po-Hung Lin

Po-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210327735
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including disposing a mask at a first position in a first chamber, generating; a first plurality of ions toward the mask by an ionizer, forming a photoresist layer on a substrate, receiving the substrate in the first chamber, and exposing the photoresist layer with actinic radiation through the mask in the first chamber.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: PO-CHIEN HUANG, CHUNG-HUNG LIN, CHIH-WEI WEN
  • Publication number: 20210327765
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, a second transistor in the first region, and a third transistor in the second region. The first transistor includes a first channel layer and a first gate dielectric layer on the first channel layer. The second transistor includes a second channel layer and a second gate dielectric layer on the second channel layer. The second gate dielectric layer is thicker than the first gate dielectric layer. The third transistor includes a third channel layer and a third gate dielectric layer on the third channel layer. The third gate dielectric layer is thicker than the second gate dielectric layer.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Pei-Hsun Wu, Ming-Hung Han, Po-Nien Chen, Chih-Yung Lin
  • Publication number: 20210328336
    Abstract: A housing for an electronic device is described. The housing comprises a molded reinforced plastic, wherein the molded reinforced plastic comprises a woven glass fiber cloth and a single epoxy resin, which is a bisphenol A epoxy resin.
    Type: Application
    Filed: November 1, 2018
    Publication date: October 21, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Po-Feng Chuang, Kun-Hung Lin, Shih-hua Chang
  • Patent number: 11145733
    Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: October 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Yu-Hsiang Lin, Po-Wen Su, Chung-Fu Chang, Guang-Yu Lo, Chun-Tsen Lu
  • Publication number: 20210304981
    Abstract: A keyswitch support connection structure incudes a bottom plate portion and a joining portion firmly joined with a joining hole of a bottom plate portion to form a support connection portion. In an embodiment, a cantilever plate extends upward from the joining hole. The joining portion encapsulates a holding structure of the cantilever plate. In another embodiment, a protruding bridge portion connected across two sides of the joining hole. The joining portion encapsulates the protruding bridge portion. In another embodiment, the joining portion has a wing portion protruding from a bottom surface of the bottom plate portion and extending parallel to the bottom surface. A keyswitch structure includes a base with the keyswitch support connection structure, a keycap, and two keyswitch supports. The two keyswitch supports are connected to and between the keycap and the base; therein, one of the keyswitch supports is rotatably connected to the support connection portion.
    Type: Application
    Filed: March 30, 2021
    Publication date: September 30, 2021
    Inventors: Po-Chun Hou, Chin-Hung Lin, Liang-Ta Yeh, Ling-Hsi Chao
  • Publication number: 20210304979
    Abstract: A keyswitch support connection structure incudes a bottom plate portion, a cantilever plate, and a joining portion. The cantilever plate extends upward from a joining hole of the bottom plate portion and has a holding structure. The joining portion and the joining hole are firmly engaged with each other. The joining portion encapsulates the holding structure. The joining portion and the bottom plate portion jointly form or the joining portion alone forms a support connection portion. A keyswitch structure includes a base, a keycap above the base, and first and second keyswitch supports connected to and between the keycap and the base. The base includes the above keyswitch support connection structure. The first keyswitch support is rotatably connected to the support connection portion.
    Type: Application
    Filed: March 30, 2021
    Publication date: September 30, 2021
    Inventors: Po-Chun Hou, Chin-Hung Lin, Liang-Ta Yeh, Ling-Hsi Chao
  • Publication number: 20210294957
    Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Inventors: Pin-Dai SUE, Po-Hsiang HUANG, Fong-Yuan CHANG, Chi-Yu LU, Sheng-Hsiung CHEN, Chin-Chou LIU, Lee-Chung LU, Yen-Hung LIN, Li-Chun TIEN, Yi-Kan CHENG
  • Patent number: 11127341
    Abstract: A light emitting module including a circuit carrier and a plurality of light emitting devices is provided. The circuit carrier includes a first circuit layer, a second circuit layer, a dielectric layer and a plurality of conductive vias. The first circuit layer and the second circuit layer are located at two opposite sides of the dielectric layer. The conductive vias pass through the dielectric layer and two opposite end portions of each of the conductive vias are respectively connected to the first circuit layer and the second circuit layer. The light emitting devices are electrically bonded to the first circuit layer. Moreover, the light emitting devices are disposed in a device disposing area of the circuit carrier and the conductive vias are arranged outside the device disposing area. A display device is also provided.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 21, 2021
    Assignee: PlayNitride Inc.
    Inventors: Yun-Li Li, Tzu-Yang Lin, Yu-Hung Lai, Po-Jen Su, Hsuan-Wei Mai
  • Patent number: 11126247
    Abstract: A method for updating a power mode parameter combination, includes identifying a current hardware combination of a client host; loading and executing a current application program; loading a default profile according to the current application program to update a current power mode parameter combination of the current hardware combination; receiving a user-defined parameter combination to update the current power mode parameter combination of the current hardware combination; correlating the current application program, the current hardware combination and the updated current power mode parameter combination to generate a current profile as an updated default profile; and transmitting the current profile to a server as a candidate profile.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 21, 2021
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Ching-Hung Chao, Hou-Yuan Lin, Mou-Ming Ma, Chun-Kun Lan, Po-Chang Tseng, Hung-Yen Chen, Chun-Yu Wang, Yih-Neng Lin
  • Publication number: 20210285476
    Abstract: In one example, a magnet-driven connector may Include a module housing and a core module disposed In the module housing. The core module may include a protruding screw and a rotary magnetizer in contact with the protruding screw to magnetically drive the protruding screw to engage or disengage with a threaded hole of a nut portion. Further, the magnet-driven connector may include an elastic member between the core module and a bottom cover of the module housing. Furthermore, the magnet-driven connector may include a low-friction film disposed between the core module and the module housing.
    Type: Application
    Filed: November 7, 2018
    Publication date: September 16, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Po-Feng Chuang, Kun-Hung Lin, Shih-Hua Chang
  • Patent number: 11120761
    Abstract: A driving substrate includes a substrate, at least one active device, a resistor, a first passivation layer and a second passivation layer. The active device including an oxide semiconductor layer and the resistor coupled to the active device are disposed on the substrate. The first passivation layer covers the active device, wherein a portion of the first passivation layer directly contacts to the oxide semiconductor layer such that the oxide semiconductor layer has a first conductivity. The second passivation layer covers the first passivation layer and the resistor, wherein a portion of the second passivation layer directly contacts to the resistor such that the resistor has a second conductivity. The first conductivity is different from the second conductivity.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 14, 2021
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Po-Hsin Lin, Xue-Hung Tsai
  • Publication number: 20210280511
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Application
    Filed: May 10, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20210272527
    Abstract: A trace structure of a display panel including a first metal layer and a second metal layer is provided. The first metal layer is configured to transmit a first voltage. The second metal layer is disposed under the first metal layer and configured to transmit a second voltage. The first metal layer and the second metal layer form the trace structure on the display panel, such that the trace structure has a capacitor structure. The trace structure is configured to connect a power input and a panel driver circuit.
    Type: Application
    Filed: March 2, 2021
    Publication date: September 2, 2021
    Applicant: E Ink Holdings Inc.
    Inventors: Xue-Hung Tsai, Wei-Tsung Chen, Po-Hsin Lin
  • Patent number: 11102406
    Abstract: A method of processing a panoramic map based on an equirectangular projection is provided. The method comprises the following steps. A first and a second equirectangular projected panoramic images are captured through at least one lens at different time, respectively. The first and the second equirectangular projected panoramic images are perspectively transformed based on at least one horizontal angle, respectively. A plurality of first and second feature points are extracted from the first and the second equirectangular projected panoramic images, respectively. A plurality of identical feature points in the first and the second feature points are tracked. A camera pose is obtained based on the identical feature points. A plurality of 3D sparse point maps, in binary format, are established based on the at least one horizontal angle. The camera pose and the 3D sparse point maps are exported to an external system through an export channel.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: August 24, 2021
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Jiun-In Guo, Po-Hung Lin
  • Publication number: 20210203843
    Abstract: A method of processing a panoramic map based on an equirectangular projection is provided. The method comprises the following steps. A first and a second equirectangular projected panoramic images are captured through at least one lens at different time, respectively. The first and the second equirectangular projected panoramic images are perspectively transformed based on at least one horizontal angle, respectively. A plurality of first and second feature points are extracted from the first and the second equirectangular projected panoramic images, respectively. A plurality of identical feature points in the first and the second feature points are tracked. A camera pose is obtained based on the identical feature points. A plurality of 3D sparse point maps, in binary format, are established based on the at least one horizontal angle. The camera pose and the 3D sparse point maps are exported to an external system through an export channel.
    Type: Application
    Filed: November 23, 2020
    Publication date: July 1, 2021
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Jiun-In GUO, Po-Hung LIN
  • Patent number: 11010528
    Abstract: A computer-implemented method for generating a layout of a design includes invoking the computer to receive a schematic representation of the design, generating a connection graph associated with the design, comparing the connection graph with a plurality of connection graphs stored in a database and selecting a layout associated with the matching connection graph in generating the layout of the design.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: May 18, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Tung-Chieh Chen, Po-Hsun Wu, Po-Hung Lin, Tsung-Yi Ho
  • Publication number: 20210116796
    Abstract: A projector includes a light source, an optical element, a wheel-type optical assembly, a light valve, and a projection lens. The wheel-type optical assembly includes a frame, a driving unit, a rotating wheel, an optical sensing element, and a light shielding structure. The driving unit is arranged on the frame and connected to the rotating wheel. The driving unit drives the rotating wheel to rotate about a rotation axis. The optical sensing element arranged on the frame senses a rotation speed of the rotating wheel. The light shielding structure connected to the frame surrounds the optical sensing element. An orthographic projection of the light shielding structure on a reference plane partially overlaps an orthographic projection of the rotation axis on the reference plane. A normal line of the reference plane is parallel to a shortest connection line between an optical axis of the optical element and the rotation axis.
    Type: Application
    Filed: October 8, 2020
    Publication date: April 22, 2021
    Applicant: Coretronic Corporation
    Inventor: Po-Hung Lin
  • Patent number: 10635771
    Abstract: A method for parasitic-aware capacitor sizing and layout generation is proposed, which is executed by a computer, the method comprising using the computer to perform the following: creating a capacitor sizing and parasitic matching sequence to represent a unit capacitor size, routing topology and routing patterns of a plural of nets in a capacitor network. Next, a shielding assignment is performed to create a number of shielding portions of each net in the plural of nets. Then, a fitness evaluation of configurations of the capacitor sizing and parasitic matching sequence is performed. A shielding net routing is performed to compensate unmatched parasitic capacitance of the configurations of the capacitor sizing and parasitic matching sequence.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: April 28, 2020
    Assignee: AnaGlobe Technology, Inc.
    Inventors: Po-Hung Lin, Vincent Weihao Hsiao, Chun-Yu Lin, Nai-Chen Chen, Yu-Tsang Hsieh
  • Publication number: 20190331390
    Abstract: A container with functions of temperature indication and thermal storage is provided. The container includes: an inner bottle containing a liquid, a thermochromic and thermal storage material layer disposed on the outer side of the inner bottle, and a first polymer layer disposed on the outer side of the thermochromic and thermal storage material layer. The thermochromic and thermal storage material layer comprises a thermal storage material and a thermochromic material. The thermal storage material is adapted to undergo a phase change for absorption or release of thermal energy. The thermochromic material is mixed in the thermal storage material and having at least two color changes depending on a temperature change. Wherein, the first polymer layer includes a wavelength-selective polymer, and the thermochromic and thermal storage material layer absorbs light passing through the first polymer layer.
    Type: Application
    Filed: August 23, 2018
    Publication date: October 31, 2019
    Inventors: Yu-Bin CHEN, Po-Hung LIN
  • Patent number: D922995
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: June 22, 2021
    Assignee: FLYTECH TECHNOLOGY CO., LTD
    Inventors: Po-Hung Lin, Yu-shan Chen, Hsuan-Chuan Wang