Patents by Inventor PO-LI SHIH

PO-LI SHIH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210109092
    Abstract: A sensor using ultrasound to detect presence and nature of analyte includes an ultrasonic element and a receptor thereon. The ultrasonic element includes a first electrode, a second electrode facing and spaced apart from the first electrode, an insulating layer between the first electrode and the second electrode, and a vibrating film between the insulating layer and the first electrode. The vibrating film carries the first electrode. A cavity is formed between the vibrating film and the insulating layer. The receptor is on a side of the first electrode away from the second electrode. The receptor can combine with a target substance in a test analyte. When the first electrode and the second electrode are applied with different voltages, certain ultrasound frequencies are generated as the vibrating film vibrates, and the presence and weight of different target substances are indicated by the changes in resonance.
    Type: Application
    Filed: March 30, 2020
    Publication date: April 15, 2021
    Inventors: HSIN-HUA LIN, WEI-CHIH CHANG, PO-LI SHIH, CHAO-CHUN YANG, I-MIN LU
  • Patent number: 10937881
    Abstract: A gas sensor with instantaneous electrical response and thus detection of gas which meets it includes a substrate, a bottom gate electrode on a surface of the substrate, an insulating layer on the surface of the substrate carrying the bottom gate electrode and completely covering the bottom gate electrode. A semiconductor layer is on a surface of the insulating layer away from the substrate. Both the source electrode and the drain electrode, spaced apart, are located on a side of the semiconductor layer away from the substrate each being coupled to the semiconductor layer. The gas sensor further includes a passivation layer covering the semiconductor layer and a top gate electrode on the passivation layer, the top gate electrode being spaced from both the source and drain electrodes. The top gate electrode is made of electrically-conductive and gas-sensitive material. A method for making same is also disclosed.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 2, 2021
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wei-Chih Chang, Hsin-Hua Lin, Po-Li Shih
  • Patent number: 10749039
    Abstract: A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: August 18, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Po-Li Shih, Wei-Chih Chang, I-Wei Wu
  • Patent number: 10727309
    Abstract: A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3).
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: July 28, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
  • Publication number: 20200209187
    Abstract: A gas sensor with instantaneous electrical response and thus detection of gas which meets it includes a substrate, a bottom gate electrode on a surface of the substrate, an insulating layer on the surface of the substrate carrying the bottom gate electrode and completely covering the bottom gate electrode. A semiconductor layer is on a surface of the insulating layer away from the substrate. Both the source electrode and the drain electrode, spaced apart, are located on a side of the semiconductor layer away from the substrate each being coupled to the semiconductor layer. The gas sensor further includes a passivation layer covering the semiconductor layer and a top gate electrode on the passivation layer, the top gate electrode being spaced from both the source and drain electrodes. The top gate electrode is made of electrically-conductive and gas-sensitive material. A method for making same is also disclosed.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 2, 2020
    Inventors: WEI-CHIH CHANG, HSIN-HUA LIN, PO-LI SHIH
  • Patent number: 10672880
    Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: June 2, 2020
    Assignees: HONG FU JIN PRECISION INDUSTRY (SheZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Wei-Chih Chang, I-Min Lu
  • Patent number: 10504927
    Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).
    Type: Grant
    Filed: December 10, 2016
    Date of Patent: December 10, 2019
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Wei-Chih Chang, I-Min Lu, I-Wei Wu
  • Publication number: 20190027505
    Abstract: A semiconductor device comprises a multi-layered structure disposed over a substrate (101) and defining a composite lateral etch profile. The multi-layered structure includes a lower sub-layer (105-1) disposed over the substrate (101) and comprising a metal oxide material that includes indium and zinc, the indium and zinc content in the lower sub-layer (105-1) substantially defining a first indium to zinc content ratio; a middle sub-layer (105-2) disposed over the lower sub-layer (105-1) and comprising a metal material; an upper sub-layer (105-3) disposed over the middle sub-layer (105-2) and comprising a metal oxide material that includes indium and zinc, the indium to zinc content in the upper sub-layer (105-3) substantially defining a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and a lateral byproduct layer formed over the lateral etched surface, comprising substantially an metal oxide of the metal material in the middle sub-layer (105-2).
    Type: Application
    Filed: December 10, 2016
    Publication date: January 24, 2019
    Applicants: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Yi-Chun KAO, Hsin-Hua LIN, Po-Li SHIH, Wei-Chih CHANG, Imin LU, Iwei WU
  • Publication number: 20190027571
    Abstract: A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.
    Type: Application
    Filed: December 10, 2016
    Publication date: January 24, 2019
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: HSIN-HUA LIN, PO-LI SHIH, YI-CHUN KAO, CHANG-CHUN WAN, WEI-CHIH CHANG, I-WEI WU
  • Publication number: 20190027506
    Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that in the first sub-layer.
    Type: Application
    Filed: December 13, 2016
    Publication date: January 24, 2019
    Inventors: PO-LI SHIH, YI-CHUN KAO, HSIN-HUA LIN, CHIH-LUNG LEE, WEI-CHIH CHANG, I-MIN LU
  • Publication number: 20190019870
    Abstract: A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3).
    Type: Application
    Filed: December 7, 2016
    Publication date: January 17, 2019
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YI-CHUN KAO, HSIN-HUA LIN, PO-LI SHIH, WEI-CHIH CHANG, I-MIN LU, I-WEI WU
  • Publication number: 20180374960
    Abstract: A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.
    Type: Application
    Filed: December 6, 2016
    Publication date: December 27, 2018
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YI-CHUN KAO, PO-LI SHIH, WEI-CHIH CHANG, I-WEI WU
  • Patent number: 10062791
    Abstract: A thin film transistor comprises a substrate, a gate electrode formed on the substrate, an electrically insulating layer covering the gate electrode, a channel layer made of a semiconductor material and formed on the electrically insulating layer, a source electrode formed on a first lateral side of the electrically insulating layer, and a drain electrode formed on an opposite second lateral side of the electrically insulating layer. The source electrode has an inner end covering a first outer end of the channel layer and electrically connecting therewith. The drain electrode has an inner end covering an opposite second outer end of the channel layer and electrically connecting therewith. An area of the channel layer adjacent to and not covered by one of the source electrode and the drain electrode has an electrical conductivity lower than the electrical conductivity of other area of the channel layer.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 28, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Po-Li Shih, Chih-Lung Lee, Hsin-Hua Lin
  • Publication number: 20180097116
    Abstract: A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.
    Type: Application
    Filed: November 23, 2017
    Publication date: April 5, 2018
    Inventors: HSIN-HUA LIN, YI-CHUN KAO, CHIH-LUNG LEE, PO-LI SHIH, KUO-LUNG FANG
  • Patent number: 9905697
    Abstract: A high-performance TFT substrate for a flat panel display includes a substrate, a first conductive layer on the substrate, a semiconductor layer positioned on the first conductive layer, and a second conductive layer positioned on the semiconductor layer. The first conductive layer defines a gate electrode. The second conductive layer defines a source electrode and a drain electrode spaced apart from the source electrode. The second conductive layer includes a first layer on the semiconductor layer and a second layer positioned on the first layer. The first layer can be made of metal oxide. The second layer can be made of aluminum or aluminum alloy.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: February 27, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Po-Li Shih, Wei-Chih Chang, I-Wei Wu
  • Patent number: 9893197
    Abstract: A thin film transistor (TFT) includes a substrate, a TFT formed on the substrate, and a passivation layer formed on the TFT. The TFT includes a gate, a source, a drain, and a channel layer. The source and the drain are respectively located at opposite sides of the channel layer. The channel layer includes oxygen ions which are implanted into the channel layer by an oxygen implanting process performed in an environment having an air pressure greater than a standard atmospheric pressure.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 13, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yi-Chun Kao, Hsin-Hua Lin, Chih-Lung Lee, Kuo-Lung Fang, Po-Li Shih
  • Patent number: 9893198
    Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 13, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Patent number: 9859440
    Abstract: A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 2, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao, Chih-Lung Lee, Po-Li Shih, Kuo-Lung Fang
  • Patent number: 9853057
    Abstract: A display array substrate includes a substrate, a plurality of gate lines and a plurality of data lines disposed on the substrate, and a plurality of gate connecting pads. Each gate connecting pad is disposed at an end of one of the gate lines. The end of each gate line is partly covered by a first insulation layer. The first insulation layer is an anodic oxide layer.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: December 26, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Po-Li Shih, Yi-Chun Kao
  • Patent number: 9823528
    Abstract: An array substrate for a liquid crystal display device includes a first storage capacitor and a second storage capacitor for increased capacitance. The first storage capacitor is formed by a first common electrode and a pixel electrode. The second storage capacitor is formed by a second common electrode and the pixel electrode.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: November 21, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wu-Liu Tsai, Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee