Patents by Inventor Po Wei Tsai

Po Wei Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651040
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: May 12, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20200135470
    Abstract: The present disclosure describes a system and a method for a ion implantation (IMP) process. The system includes an ion implanter configured to scan an ion beam over a target for a range of angles, a tilting mechanism configured to support and tilt the target, an ion-collecting device configured to collect a distribution and a number of ejected ions from the ion beam scan over the target, and a control unit configured to adjust a tilt angle based on a correction angle determined based on the distribution and number of ejected ions.
    Type: Application
    Filed: April 11, 2019
    Publication date: April 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Jung HUANG, Li-Hsin CHU, Po-Feng TSAI, Henry PENG, Kuang Huan HSU, Tsung Wei CHEN, Yung-Lin HSU
  • Publication number: 20200105644
    Abstract: A semiconductor device includes a chip package comprising a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die having an active surface, a back surface opposite to the active surface, and a thermal enhancement pattern on the back surface; and a heat dissipation structure connected to the chip package, the heat dissipation structure comprising a heat spreader having a flow channel for a cooling liquid, and the cooling liquid in the flow channel being in contact with the thermal enhancement pattern.
    Type: Application
    Filed: August 7, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Chen-Hua Yu, Hao-Yi Tsai, Kuo-Chung Yee, Tin-Hao Kuo, Shih-Wei Chen
  • Publication number: 20200105763
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Publication number: 20200105663
    Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 2, 2020
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 10529719
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: January 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Publication number: 20200006214
    Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.
    Type: Application
    Filed: August 31, 2018
    Publication date: January 2, 2020
    Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
  • Publication number: 20200006307
    Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.
    Type: Application
    Filed: November 16, 2018
    Publication date: January 2, 2020
    Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
  • Publication number: 20200006176
    Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.
    Type: Application
    Filed: November 26, 2018
    Publication date: January 2, 2020
    Inventors: Po-Hao TSAI, Techi WONG, Meng-Wei CHOU, Meng-Liang LIN, Po-Yao CHUANG, Shin-Puu JENG
  • Patent number: 10505437
    Abstract: A power converting device includes a DC-DC converting circuit, a DC-AC converting circuit, and an insulation detecting circuit. The DC-DC converting circuit is configured to convert a DC input voltage to a DC bus voltage. The DC-AC converting circuit is electrically coupled to the DC-DC converting circuit and configured to convert the DC bus voltage to an AC voltage. The insulation detecting circuit is electrically coupled between the DC-DC converting circuit and the DC-AC converting circuit. The insulation detecting circuit is configured to detect a ground impedance value of the power converting device according to the DC bus voltage.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: December 10, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Tsung-Han Tsai, Po-Jen Hou, Chen-Wei Ku, Xin-Hung Lin
  • Publication number: 20190322762
    Abstract: An antibody, or an antigen-binding fragment there, binding human ENO1 (GenBank: AAH506421.1) is provided. Methods for treating an ENO1 protein-related disease or disorder, inhibiting cancer invasion and diagnosis of cancer are also provided.
    Type: Application
    Filed: March 19, 2018
    Publication date: October 24, 2019
    Applicants: DEVELOPMENT CENTER FOR BIOTECHNOLOGY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: SHIH-CHONG TSAI, TA-TUNG YUAN, SHIH-CHI TSENG, JIANN-SHIUN LAI, CHIA-CHENG WU, PO-YIN LIN, YA-WEI TSAI, CHAO-YANG HUANG, YING-YUNG LOK, CHUNG-HSIUN WU, HSIEN-YU TSAI, NENG-YAO SHIH, KO-JIUNN LIU, LI-TZONG CHEN
  • Patent number: 10453805
    Abstract: A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 22, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin
  • Publication number: 20190318933
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Application
    Filed: May 22, 2018
    Publication date: October 17, 2019
    Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
  • Publication number: 20190298848
    Abstract: The invention relates to antibody fusion proteins. Particularly, the invention relates to antibody fusion proteins for intra-cellular and intra-nucleus drugs delivery. The fusion protein of the invention can be used as a peptide penetration system that specifically binds to various targets for the delivery of effector peptides across a biological barrier.
    Type: Application
    Filed: June 6, 2017
    Publication date: October 3, 2019
    Inventors: Min-che CHEN, Ya-chuan LIU, Po-hao CHANG, Ya-ping TSAI, Chun-wei CHEN, Pei-yi LEE
  • Publication number: 20190296019
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Application
    Filed: April 24, 2018
    Publication date: September 26, 2019
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Publication number: 20190280095
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
    Type: Application
    Filed: April 3, 2018
    Publication date: September 12, 2019
    Inventors: Po-Chun Chen, Chia-Lung Chang, Yi-Wei Chen, Wei-Hsin Liu, Han-Yung Tsai
  • Publication number: 20190221384
    Abstract: A keyswitch structure includes a base plate, a keycap, a first support, and a second support. The keycap is located above the base plate. The first support is connected to and between the keycap and the base plate and has an upper connection portion, a lower connection portion, and a protruding limitation portion. The upper connection portion is located between the lower connection portion and the protruding limitation portion. The first support is rotatably connected to the keycap and the base plate through the upper connection portion and the lower connection portion respectively. The protruding limitation portion is located close to and under the cap body. The second support is connected to and between the keycap and the base plate. The keycap moves up and down relative to the base plate through the first support and the second support.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 18, 2019
    Inventors: Chih-Hao Chen, Po-Wei Tsai, Chun-Yuan Wang, Kuan-Te Lin, Shao-Wei Yang, Ling-Hsi Chao
  • Patent number: 10298203
    Abstract: A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin
  • Publication number: 20190143053
    Abstract: An aerosol generating apparatus includes a vial, a cap assembly and a receptacle. The vial stores liquid medicament and includes a puncturable seal held in position by a retaining ring. The cap assembly includes an actuator with an interior bore extending therethrough, a perforated membrane coupled to the actuator, a fastener and a first mating element. The fastener is adapted to detachably secure the cap assembly to the vial such that the perforated membrane aligns with the puncturable seal. The receptacle receives the cap assembly with the vial. The receptacle includes a driving element and a second mating element capable of mating with the first mating element. The driving element aligns and communicates with the perforated membrane when the receptacle engages the cap assembly. The actuator pierces the puncturable seal to displace the liquid medicament through the interior bore to the perforated membrane and the driving element to generate aerosol.
    Type: Application
    Filed: December 5, 2017
    Publication date: May 16, 2019
    Inventors: Yi-Tong Chen, Chih-Wei Lu, Ting-Kai Tsai, Po-Chuan Chen
  • Patent number: 10290610
    Abstract: A PoP device includes a first package structure, a second package structure and an underfill layer is provided. The first package structure includes a die, a TIV and an encapsulant. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and a portion of sidewalls of the TIV. The second package structure is connected to the first package structure through a connector. The underfill layer is disposed to fill a space between the first package structure and the second package structure. A portion of the underfill layer is disposed between the encapsulant and the TIV to cover a portion of sidewalls of the TIV.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Li-Hui Cheng, Po-Hao Tsai, Wei-Yu Chen, Ming-Shih Yeh