Patents by Inventor Po-Yung Chang

Po-Yung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10283196
    Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of a rewritable non-volatile memory module at least into a first area and a second area, wherein the second area is programmed with a single-page programming mode and the first area is programmed with a multi-page programming mode. The method further includes receiving first data; and determining whether the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value, and if yes, writing the first data into the physical erasing units of the second area.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 7, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Po-Yung Chang
  • Publication number: 20170365334
    Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of a rewritable non-volatile memory module at least into a first area and a second area, wherein the second area is programmed with a single-page programming mode and the first area is programmed with a multi-page programming mode. The method further includes receiving first data; and determining whether the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value, and if yes, writing the first data into the physical erasing units of the second area.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 21, 2017
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Po-Yung Chang
  • Patent number: 9383995
    Abstract: Techniques are disclosed relating to ordering of load instructions in a weakly-ordered memory model. In one embodiment, a processor includes a cache with multiple cache lines and a store queue configured to maintain status information associated with a store instruction that targets a location in one of the cache lines. In this embodiment, the processor is configured to set an indicator in the status information in response to migration of the targeted cache line. The indicator may be usable to sequence performance of load instructions that are younger than the store instruction. For example, the processor may be configured to wait, based on the indicator, to perform a younger load instruction that targets the same location as the store instruction until the store instruction is removed from the store queue. This may prevent forwarding of the value of the store instruction to the younger load and preserve load-load ordering.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: July 5, 2016
    Assignee: Apple Inc.
    Inventors: Pradeep Kanapathipillai, Hari Kannan, Po-Yung Chang, Ming-Ta Hsu, Rajat Goel
  • Patent number: 8892841
    Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: November 18, 2014
    Assignee: Apple Inc.
    Inventors: Ramesh Gunna, Po-Yung Chang, Sudarshan Kadambi
  • Publication number: 20140215191
    Abstract: Techniques are disclosed relating to ordering of load instructions in a weakly-ordered memory model. In one embodiment, a processor includes a cache with multiple cache lines and a store queue configured to maintain status information associated with a store instruction that targets a location in one of the cache lines. In this embodiment, the processor is configured to set an indicator in the status information in response to migration of the targeted cache line. The indicator may be usable to sequence performance of load instructions that are younger than the store instruction. For example, the processor may be configured to wait, based on the indicator, to perform a younger load instruction that targets the same location as the store instruction until the store instruction is removed from the store queue. This may prevent forwarding of the value of the store instruction to the younger load and preserve load-load ordering.
    Type: Application
    Filed: January 25, 2013
    Publication date: July 31, 2014
    Applicant: APPLE INC.
    Inventors: Pradeep Kanapathipillai, Hari Kannan, Po-Yung Chang, Ming-Ta Hsu, Rajat Goel
  • Patent number: 8316188
    Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache. In an embodiment, the prefetch unit is configured to check for a cache hit for a prefetch request by checking a duplicate cache tags.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: November 20, 2012
    Assignee: Apple Inc.
    Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
  • Publication number: 20120278685
    Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.
    Type: Application
    Filed: July 9, 2012
    Publication date: November 1, 2012
    Inventors: Ramesh Gunna, Po-Yung Chang, Sudarshan Kadambi
  • Patent number: 8285937
    Abstract: In an embodiment, a processor may be configured to detect a store exclusive operation followed by a memory barrier operation in a speculative instruction stream being executed by the processor. The processor may fuse the store exclusive operation and the memory barrier operation, creating a fused operation. The fused operation may be transmitted and globally ordered, and the processor may complete both the store exclusive operation and the memory barrier operation in response to the fused operation. As the fused operation progresses through the processor and one or more other components (e.g. caches in the cache hierarchy) to the ordering point in the system, the fused operation may push previous memory operations to effect the memory barrier operation. In some embodiments, the latency for completing the store exclusive operation and the subsequent data memory barrier operation may be reduced if the store exclusive operation is successful at the ordering point.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: October 9, 2012
    Assignee: Apple Inc.
    Inventors: Peter J. Bannon, Po-Yung Chang
  • Patent number: 8255670
    Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: August 28, 2012
    Assignee: Apple Inc.
    Inventors: Po-Yung Chang, Wei-Han Lien, Jesse Pan, Ramesh Gunna, Tse-Yu Yeh, James B. Keller
  • Patent number: 8239638
    Abstract: In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: August 7, 2012
    Assignee: Apple Inc.
    Inventors: Ramesh Gunna, Po-Yung Chang, Sudarshan Kadambi
  • Patent number: 8219787
    Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: July 10, 2012
    Assignee: Apple Inc.
    Inventors: Wei-Han Lien, Po-Yung Chang
  • Publication number: 20120110392
    Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Inventors: Tse-Yu Yeh, Po-Yung Chang, Eric Hao
  • Patent number: 8171240
    Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: May 1, 2012
    Assignee: Apple Inc.
    Inventors: Tse-Yu Yeh, Po-Yung Chang, Eric Hao
  • Patent number: 8117404
    Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: February 14, 2012
    Assignee: Apple Inc.
    Inventors: Tse-Yu Yeh, Po-Yung Chang, Eric Hao
  • Publication number: 20110264864
    Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 27, 2011
    Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
  • Publication number: 20110214127
    Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
    Type: Application
    Filed: May 9, 2011
    Publication date: September 1, 2011
    Inventors: Wei-Han Lien, Po-Yung Chang
  • Publication number: 20110208915
    Abstract: In an embodiment, a processor may be configured to detect a store exclusive operation followed by a memory barrier operation in a speculative instruction stream being executed by the processor. The processor may fuse the store exclusive operation and the memory barrier operation, creating a fused operation. The fused operation may be transmitted and globally ordered, and the processor may complete both the store exclusive operation and the memory barrier operation in response to the fused operation. As the fused operation progresses through the processor and one or more other components (e.g. caches in the cache hierarchy) to the ordering point in the system, the fused operation may push previous memory operations to effect the memory barrier operation. In some embodiments, the latency for completing the store exclusive operation and the subsequent data memory barrier operation may be reduced if the store exclusive operation is successful at the ordering point.
    Type: Application
    Filed: February 24, 2010
    Publication date: August 25, 2011
    Inventors: Peter J. Bannon, Po-Yung Chang
  • Patent number: 7996646
    Abstract: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 9, 2011
    Assignee: Apple Inc.
    Inventors: Tse-yu Yeh, Daniel C. Murray, Po-Yung Chang, Anup S. Mehta
  • Patent number: 7996624
    Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: August 9, 2011
    Assignee: Apple Inc.
    Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
  • Patent number: 7984274
    Abstract: In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: July 19, 2011
    Assignee: Apple Inc.
    Inventors: Sudarshan Kadambi, Po-Yung Chang, Eric Hao