Patents by Inventor Po-Zen Chen

Po-Zen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080227288
    Abstract: A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.
    Type: Application
    Filed: March 15, 2007
    Publication date: September 18, 2008
    Inventors: Po-Zen Chen, Tzu-Chan Weng, Chien-Chung Chen
  • Publication number: 20080083710
    Abstract: A adjustable upper coil or electrode for a reaction chamber apparatus useable in semiconductor processing, is constructed so that its shape may be selectively changed or so at least two portions thereof may be selectively driven at different power and/or frequencies. The adjustable upper coil or electrode, therefore, enables the plasma density distribution in the reaction chamber apparatus to be selectively controlled.
    Type: Application
    Filed: September 22, 2006
    Publication date: April 10, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Lin Chen, Chi-An Kao, Po-Zen Chen, Yi-Li Hsiao, Chen-Hua Yu, Jean Wang, Lawrance Sheu
  • Publication number: 20070020777
    Abstract: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.
    Type: Application
    Filed: July 25, 2005
    Publication date: January 25, 2007
    Inventors: Chia-Tsung Tso, Jiun-Hong Lai, Mei-Jen Wu, Li Hsu, Pin Su, Po-Zen Chen
  • Publication number: 20040054642
    Abstract: A system for decoding and searching the content of a file and the operation method thereof are disclosed, wherein the present invention is utilized in an automated material handling system (AMHS). By utilizing the present invention, the lot historical record file is downloaded at a predetermined time, and then a decoding device is utilized to decode the content of the lot historical record file and a decoded result is obtained. The decoded result will be stored in an online database, so that the staff can search and check the content of the lot historical record file by connecting to the online database in internet information service through internet or other ways. Therefore, not only the searching speed is rapid, but also the loading of the AMHS is not increased. Meanwhile, wherever the maintainer is, he can maintain the lot historical record file through internet in any time.
    Type: Application
    Filed: September 17, 2002
    Publication date: March 18, 2004
    Inventor: Po-Zen Chen