Patents by Inventor Pouya Hashemi

Pouya Hashemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210193920
    Abstract: A resistive random access memory (RRAM) structure includes top and bottom electrodes electrically coupled with first and second metal connection lines, respectively, the first and second metal connection lines providing electrical connection to the RRAM structure. A layer of resistive switching material is disposed between the top and bottom electrodes of the RRAM structure. The resistive switching material exhibits a measurable change in resistance under influence of at least an electric field and/or heat. Dielectric spacers are formed on sidewalls of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer formed on an upper surface of the dielectric spacers and covering at least a portion of sidewalls of the top electrode. The passivation layer is self-aligned with the first metal connection line.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Takashi Ando, Ruilong Xie, Pouya Hashemi, Alexander Reznicek
  • Patent number: 11043587
    Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: June 22, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Publication number: 20210183710
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.
    Type: Application
    Filed: February 3, 2021
    Publication date: June 17, 2021
    Inventors: Takashi Ando, Choonghyun Lee, Pouya Hashemi, Jingyun Zhang
  • Patent number: 11037986
    Abstract: A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek, Choonghyun Lee
  • Patent number: 11038103
    Abstract: A semiconductor structure includes an oxide ReRAM co-integrated with a drain region of a field effect transistor (FET). The oxide ReRAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide ReRAM and thus helps to control forming of the conductive filament of the oxide ReRAM.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Takashi Ando, Pouya Hashemi
  • Patent number: 11037832
    Abstract: Semiconductor devices and methods of forming the same include partially etching sacrificial layers in a first stack of alternating sacrificial layers and channel layers to form first recesses. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers are etched away. The first inner spacer sub-layer is etched away. A gate stack is formed on and around the channel layers and in contact with the second inner spacer sub-layer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Patent number: 11031297
    Abstract: Various embodiments disclose a method for fabricating a semiconductor structure. In one embodiment, the method includes forming a masking layer over at least a first portion of a source contact layer formed on a substrate. At least a second portion of the source contact layer is recessed below the first portion of the source contact layer. The mask layer is removed and a first spacer layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer are formed. First and second trenches are then formed. A first channel layer is epitaxially grown within the first trench. A second channel layer is epitaxially grown within the second trench. A length of the second channel layer is greater than a length of the first channel layer.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 11024740
    Abstract: A SiGe channel FinFET structure has an asymmetric threshold voltage, Vth, laterally along the SiGe channel. Uses of sacrificial layers, selective Ge condensation, and/or the use of spacers enable precise creation of first and second channel regions with different Ge concentration, even for channels with short lengths. The second channel region near the source side of the device is modified with a selective Germanium (Ge) condensation to have a higher Vth than the first channel region near the drain side. A lateral electric field is created in the channel to enhance carrier mobility.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Takashi Ando, Alexander Reznicek, Jingyun Zhang, Pouya Hashemi
  • Patent number: 11024724
    Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang, Pouya Hashemi
  • Patent number: 11018062
    Abstract: A method of fabricating a semiconductor device includes providing a high-k dielectric layer arranged on a channel region including a first transistor area and a second transistor area. The method further includes depositing a multivalent oxide layer directly on the high-k dielectric layer of the first transistor area. The method includes depositing a first work function metal on the multivalent oxide layer of the first transistor area and directly on the high-k dielectric layer of the second transistor area.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang, Pouya Hashemi
  • Patent number: 11018254
    Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 11018192
    Abstract: Embodiments of the invention include resulting structures and a method for fabricating a vertical ReRAM array structure. The embodiments of the invention include forming alternating layers over a metal layer of a structure, wherein a layer of the alternating layers comprises a low resistivity material, masking one or more portions of a topmost layer of the alternating layers, and etching one or more portions of the alternating layers down to the metal layer. Embodiments of the invention also include depositing a lateral electrode layer over the etched one or more portions of the alternating layers, performing an etch back on the lateral electrode layer, and forming a vertical electrode layer over the structures.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • Publication number: 20210151503
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The structure is a MRAM element having a first conductive electrode embedded in a first interconnect dielectric material layer upon which a multi-layered magnetic tunnel junction (MTJ) memory element is formed in a magnetoresistive random access memory (MRAM) device area. The first conductive electrode includes a first end having a top surface of a first surface area and a second end having a bottom surface of a second surface area, the first surface area being smaller than the second surface area. The second end of the bottom electrode includes a barrier liner material including a metal fill material, and the first end of the bottom electrode is a pillar structure formed as a result of an etchback process in which the metal barrier liner is recessed relative to the metal fill material.
    Type: Application
    Filed: December 29, 2020
    Publication date: May 20, 2021
    Inventors: Pouya Hashemi, Bruce B.` Doris, Chandrasekharan Kothandaraman, Nathan P. Marchack
  • Patent number: 10998419
    Abstract: Bipolar junction transistor structures and methods for making the same are provide. The method includes: providing a substrate with an insulator layer and a device layer over the insulator layer, forming an intrinsic base from the device layer, forming emitter and collector regions from the device layer, and after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Tak Ning, Jeng-Bang Yau, Alexander Reznicek
  • Publication number: 20210126122
    Abstract: A semiconductor device includes a semiconductor substrate and a field effect transistor disposed on the semiconductor substrate. The field effect transistor includes a vertical fin defining a longitudinal length along a first axis, a width along a second axis and a vertical height along a third axis. The vertical fin includes source and drain regions separated by a gate region and a gate structure over the gate region. The gate structure includes a dipole layer and a gate electrode layer over the dipole layer. A first longitudinal section of the gate structure includes the dipole layer and a second longitudinal section of the gate structure is devoid of the dipole layer.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: Takashi Ando, Alexander Reznicek, Pouya Hashemi, Ruilong Xie
  • Patent number: 10991823
    Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: April 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Publication number: 20210118683
    Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.
    Type: Application
    Filed: December 29, 2020
    Publication date: April 22, 2021
    Inventors: Jingyun Zhang, Choonghyun Lee, Takashi Ando, Alexander Reznicek, Pouya Hashemi
  • Publication number: 20210119121
    Abstract: A bottom electrode structure for a magnetic tunnel junction (MTJ) containing device is provided. The bottom electrode structure includes a mesa portion that is laterally surrounded by a recessed region. The recessed region of the bottom electrode structure is laterally adjacent to a dielectric material, and a MTJ pillar is located on the mesa portion of the bottom electrode structure. Such a configuration shields the recessed region from impinging ions thus preventing deposition of resputtered conductive metal particles from the bottom electrode onto the MTJ pillar.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Inventors: Nathan P. Marchack, Bruce B. Doris, Pouya Hashemi
  • Publication number: 20210111255
    Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. A gate stack is formed on the semiconductor fin, between the outer spacers.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Inventors: Takashi Ando, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Patent number: 10971407
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Choonghyun Lee, Pouya Hashemi, Jingyun Zhang