Patents by Inventor Pradeep Ramachandramurthy Yelehanka
Pradeep Ramachandramurthy Yelehanka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150048509Abstract: A wafer bonding layer and a process for using the same for bonding wafers are presented. The wafer bonding process includes providing a first wafer, providing a second type wafer and providing a water bonding layer. The wafer bonding layer is provided separately on a contact surface layer of the first or second wafer as part of a CMOS compatible processing recipe.Type: ApplicationFiled: August 14, 2014Publication date: February 19, 2015Inventors: Ranganathan NAGARAJAN, Fu Chuen TAN, Kia Hwee Samuel LOW, Chun Hoe YIK, Jiaqi WU, Jingze TIAN, Pradeep Ramachandramurthy YELEHANKA, Rakesh KUMAR
-
Patent number: 8536705Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.Type: GrantFiled: April 25, 2012Date of Patent: September 17, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
-
Patent number: 8513767Abstract: A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type.Type: GrantFiled: March 21, 2011Date of Patent: August 20, 2013Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Pradeep Ramachandramurthy Yelehanka
-
Patent number: 8394724Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.Type: GrantFiled: August 22, 2007Date of Patent: March 12, 2013Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Hai Cong, Wei Loong Loh, Krishan Gopal, Xin Zhang, Mei Sheng Zhou, Pradeep Ramachandramurthy Yelehanka
-
Publication number: 20130034954Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: ApplicationFiled: October 8, 2012Publication date: February 7, 2013Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
-
Patent number: 8304834Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.Type: GrantFiled: August 22, 2006Date of Patent: November 6, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Pradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
-
Patent number: 8283263Abstract: An integrated circuit method for manufacturing an integrated circuit system including loading a wafer into a processing chamber and pre-purging the processing chamber with a first ammonia gas. Depositing a first nitride layer over the wafer and purging the processing chamber with a second ammonia gas. Depositing a second nitride layer over the first nitride layer that is misaligned with the first nitride layer. Post-purging the processing chamber with a third ammonia gas and purging the processing chamber with a nitrogen gas.Type: GrantFiled: July 5, 2006Date of Patent: October 9, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sripad Sheshagiri Nagarad, Hwa Weng Koh, Dong Kyun Sohn, Xiaoyu Chen, Louis Lim, Sung Mun Jung, Chiew Wah Yap, Pradeep Ramachandramurthy Yelehanka, Nitin Kamat
-
Publication number: 20120241901Abstract: A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type.Type: ApplicationFiled: March 21, 2011Publication date: September 27, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Pradeep Ramachandramurthy YELEHANKA
-
Publication number: 20120205806Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.Type: ApplicationFiled: April 25, 2012Publication date: August 16, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Pradeep Ramachandramurthy YELEHANKA, Denise TAN, Chung Meng LEK, Thomas THIAM, Jeffrey C. LAM, Liang-Choo HSIA
-
Patent number: 8236646Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.Type: GrantFiled: November 6, 2003Date of Patent: August 7, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Tze Ho Simon Chan, Weining Li, Elgin Quek, Jia Zhen Zheng, Pradeep Ramachandramurthy Yelehanka, Tommy Lai
-
Patent number: 8236688Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.Type: GrantFiled: June 13, 2011Date of Patent: August 7, 2012Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
-
Publication number: 20110237072Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.Type: ApplicationFiled: June 13, 2011Publication date: September 29, 2011Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
-
Patent number: 7964894Abstract: An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization.Type: GrantFiled: May 20, 2010Date of Patent: June 21, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka
-
Patent number: 7960282Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.Type: GrantFiled: May 21, 2009Date of Patent: June 14, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
-
Publication number: 20100297844Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.Type: ApplicationFiled: May 21, 2009Publication date: November 25, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
-
Publication number: 20100230765Abstract: An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization.Type: ApplicationFiled: May 20, 2010Publication date: September 16, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka
-
Patent number: 7759207Abstract: An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the integrated circuit system; and transferring a stress from the stress memorization layer to the gate and the source/drain region.Type: GrantFiled: March 21, 2007Date of Patent: July 20, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka
-
Patent number: 7501683Abstract: An integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.Type: GrantFiled: May 30, 2006Date of Patent: March 10, 2009Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Tommy Lai, Pradeep Ramachandramurthy Yelehanka, Jia Zhen Zheng, Weining Li
-
Publication number: 20080230841Abstract: An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the integrated circuit system; and transferring a stress from the stress memorization layer to the gate and the source/drain region.Type: ApplicationFiled: March 21, 2007Publication date: September 25, 2008Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka
-
Publication number: 20080054477Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.Type: ApplicationFiled: August 22, 2007Publication date: March 6, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Hai CONG, Wei Loong LOH, Krishan GOPAL, Xin ZHANG, Mei Sheng ZHOU, Pradeep Ramachandramurthy YELEHANKA