Patents by Inventor Pradipta Patra

Pradipta Patra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11451084
    Abstract: Disclosed are electronic devices including a polymer including a ferroelectric and quantum dots disposed in the ferroelectric, at least one solar cell configured to receive light through the polymer and to convert the light into electrical energy, and a battery configured to be charged with the electrical energy from the at least one solar cell.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jun Park, Jae-Hyun Park, Pradipta Patra
  • Patent number: 11068006
    Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Chepuri
  • Patent number: 10990146
    Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Ramnarayanan Muthukaruppan, Pradipta Patra, Gaurav Goel, Uday Bhaskar Kadali
  • Patent number: 10707690
    Abstract: An electronic device for charging a battery is provided. The electronic device includes a first path configured to receive a first power of a first voltage from an adapter, a second path configured to receive a second power of a second voltage from the adapter, a charger, connected to the first path, configured to receive the first power, adjust at least one of a voltage or a current of the first power, and provide the adjusted first power to the battery; and a processor configured to control to connect the second path to the battery during fast charging to directly connect the battery to the adapter.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Jung, Bong-Chul Kim, Pradipta Patra, Ki-Young Kim, Yun-Kwon Park
  • Publication number: 20190235557
    Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Inventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Chepuri
  • Publication number: 20190220074
    Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 18, 2019
    Inventors: Ramnarayanan MUTHUKARUPPAN, Pradipta PATRA, Gaurav GOEL, Uday Bhaskar KADALI
  • Patent number: 10345881
    Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali
  • Patent number: 10268249
    Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Ramnarayanan Muthukaruppan, Pradipta Patra, Gaurav Goel, Uday Bhaskar Kadali
  • Patent number: 10185382
    Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali
  • Publication number: 20180337551
    Abstract: Disclosed are electronic devices including a polymer including a ferroelectric and quantum dots disposed in the ferroelectric, at least one solar cell configured to receive light through the polymer and to convert the light into electrical energy, and a battery configured to be charged with the electrical energy from the at least one solar cell.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 22, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Jun PARK, Jae-Hyun PARK, Pradipta PATRA
  • Publication number: 20180102663
    Abstract: An electronic device for charging a battery is provided. The electronic device includes a first path configured to receive a first power of a first voltage from an adapter, a second path configured to receive a second power of a second voltage from the adapter, a charger, connected to the first path, configured to receive the first power, adjust at least one of a voltage or a current of the first power, and provide the adjusted first power to the battery; and a processor configured to control to connect the second path to the battery during fast charging to directly connect the battery to the adapter.
    Type: Application
    Filed: September 27, 2017
    Publication date: April 12, 2018
    Inventors: Ji-Hoon JUNG, Bong-Chul KIM, Pradipta PATRA, Ki-Young KIM, Yun-Kwon PARK
  • Publication number: 20170322581
    Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 9, 2017
    Inventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Nandan Chepuri
  • Publication number: 20170315601
    Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 2, 2017
    Inventors: Ramnarayanan MUTHUKARUPPAN, Harish K. KRISHNAMURTHY, Mohit VERMA, Pradipta PATRA, Uday Bhaskar KADALI
  • Patent number: 9766678
    Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali
  • Patent number: 9651978
    Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Nandan Chepuri
  • Publication number: 20170031411
    Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
    Type: Application
    Filed: October 12, 2016
    Publication date: February 2, 2017
    Inventors: Ramnarayanan MUTHUKARUPPAN, Harish K. KRISHNAMURTHY, Mohit VERMA, Pradipta PATRA, Uday Bhaskar KADALI
  • Publication number: 20160306374
    Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 20, 2016
    Inventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Nandan Chepuri
  • Publication number: 20160246342
    Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
    Type: Application
    Filed: December 18, 2013
    Publication date: August 25, 2016
    Inventors: Ramnarayanan MUTHUKARUPPAN, Pradipta PATRA, Gaurav GOEL, Uday Bhaskar KADALI
  • Publication number: 20140223205
    Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Inventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali