Patents by Inventor Pradipta Patra
Pradipta Patra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11451084Abstract: Disclosed are electronic devices including a polymer including a ferroelectric and quantum dots disposed in the ferroelectric, at least one solar cell configured to receive light through the polymer and to convert the light into electrical energy, and a battery configured to be charged with the electrical energy from the at least one solar cell.Type: GrantFiled: May 15, 2018Date of Patent: September 20, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Jun Park, Jae-Hyun Park, Pradipta Patra
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Patent number: 11068006Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.Type: GrantFiled: April 5, 2019Date of Patent: July 20, 2021Assignee: Intel CorporationInventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Chepuri
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Patent number: 10990146Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.Type: GrantFiled: March 20, 2019Date of Patent: April 27, 2021Assignee: Intel CorporationInventors: Ramnarayanan Muthukaruppan, Pradipta Patra, Gaurav Goel, Uday Bhaskar Kadali
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Patent number: 10707690Abstract: An electronic device for charging a battery is provided. The electronic device includes a first path configured to receive a first power of a first voltage from an adapter, a second path configured to receive a second power of a second voltage from the adapter, a charger, connected to the first path, configured to receive the first power, adjust at least one of a voltage or a current of the first power, and provide the adjusted first power to the battery; and a processor configured to control to connect the second path to the battery during fast charging to directly connect the battery to the adapter.Type: GrantFiled: September 27, 2017Date of Patent: July 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hoon Jung, Bong-Chul Kim, Pradipta Patra, Ki-Young Kim, Yun-Kwon Park
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Publication number: 20190235557Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 5, 2019Publication date: August 1, 2019Inventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Chepuri
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Publication number: 20190220074Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.Type: ApplicationFiled: March 20, 2019Publication date: July 18, 2019Inventors: Ramnarayanan MUTHUKARUPPAN, Pradipta PATRA, Gaurav GOEL, Uday Bhaskar KADALI
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Patent number: 10345881Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: GrantFiled: July 19, 2017Date of Patent: July 9, 2019Assignee: Intel CorporationInventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali
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Patent number: 10268249Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.Type: GrantFiled: December 18, 2013Date of Patent: April 23, 2019Assignee: INTEL CORPORATIONInventors: Ramnarayanan Muthukaruppan, Pradipta Patra, Gaurav Goel, Uday Bhaskar Kadali
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Patent number: 10185382Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: GrantFiled: October 12, 2016Date of Patent: January 22, 2019Assignee: Intel CorporationInventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali
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Publication number: 20180337551Abstract: Disclosed are electronic devices including a polymer including a ferroelectric and quantum dots disposed in the ferroelectric, at least one solar cell configured to receive light through the polymer and to convert the light into electrical energy, and a battery configured to be charged with the electrical energy from the at least one solar cell.Type: ApplicationFiled: May 15, 2018Publication date: November 22, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Jun PARK, Jae-Hyun PARK, Pradipta PATRA
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Publication number: 20180102663Abstract: An electronic device for charging a battery is provided. The electronic device includes a first path configured to receive a first power of a first voltage from an adapter, a second path configured to receive a second power of a second voltage from the adapter, a charger, connected to the first path, configured to receive the first power, adjust at least one of a voltage or a current of the first power, and provide the adjusted first power to the battery; and a processor configured to control to connect the second path to the battery during fast charging to directly connect the battery to the adapter.Type: ApplicationFiled: September 27, 2017Publication date: April 12, 2018Inventors: Ji-Hoon JUNG, Bong-Chul KIM, Pradipta PATRA, Ki-Young KIM, Yun-Kwon PARK
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Publication number: 20170322581Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.Type: ApplicationFiled: May 15, 2017Publication date: November 9, 2017Inventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Nandan Chepuri
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Publication number: 20170315601Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Inventors: Ramnarayanan MUTHUKARUPPAN, Harish K. KRISHNAMURTHY, Mohit VERMA, Pradipta PATRA, Uday Bhaskar KADALI
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Patent number: 9766678Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: GrantFiled: February 4, 2013Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali
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Patent number: 9651978Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.Type: GrantFiled: April 17, 2015Date of Patent: May 16, 2017Assignee: Intel CorporationInventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Nandan Chepuri
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Publication number: 20170031411Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: ApplicationFiled: October 12, 2016Publication date: February 2, 2017Inventors: Ramnarayanan MUTHUKARUPPAN, Harish K. KRISHNAMURTHY, Mohit VERMA, Pradipta PATRA, Uday Bhaskar KADALI
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Publication number: 20160306374Abstract: Described are apparatuses and methods for power management. The apparatus may include a power gate including a plurality of current sources. The power gate may be coupled to a load. The apparatus may further include a voltage control circuit, coupled to the power gate, to determine and select one or more current sources of the plurality of current sources to supply to the load. The apparatus may further include a current control circuit, coupled to the voltage control circuit, to control individual current sources of the one or more current sources to output a constant current. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: Rupak Ghayal, Pradipta Patra, Ramnarayanan Muthukaruppan, Raghu Nandan Chepuri
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Publication number: 20160246342Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.Type: ApplicationFiled: December 18, 2013Publication date: August 25, 2016Inventors: Ramnarayanan MUTHUKARUPPAN, Pradipta PATRA, Gaurav GOEL, Uday Bhaskar KADALI
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Publication number: 20140223205Abstract: Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Inventors: Ramnarayanan Muthukaruppan, Harish K. Krishnamurthy, Mohit Verma, Pradipta Patra, Uday Bhaskar Kadali