Patents by Inventor Praful Jain

Praful Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single event upset enhanced architecture
    Patent number: 9054684
    Abstract: A circuit block within an integrated circuit includes a multiplexor (225, 625) configured to pass either a first signal or a second signal, wherein the first signal is independent of the second signal. The circuit block further includes a first flip-flop (210, 610) configured to receive an output of the multiplexor and a second flip-flop (215, 615) configured to receive the second signal. In a first mode of operation, the multiplexor passes the first signal to the first flip-flop. Further, the first flip flop and the second flip-flop operate independently of one another. In a second mode of operation, the multiplexor passes the second signal to the first flip-flop. Further, the first flip-flop and the second flip-flop both receive the second signal.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: June 9, 2015
    Assignee: XILINX, INC.
    Inventors: Santosh Kumar Sood, Praful Jain, Ramakrishna K. Tanikella
  • Reduction of single event upsets within a semiconductor integrated circuit
    Patent number: 9000529
    Abstract: A circuit includes a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate and an n-well implemented within the p-type substrate that is independent of the storage element. The n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: April 7, 2015
    Assignee: Xilinx, Inc.
    Inventors: Praful Jain, James Karp, Michael J. Hart, Ramakrishna K. Tanikella