Patents by Inventor Prasad Chalasani

Prasad Chalasani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10037540
    Abstract: A marketplace diagnostics framework for analyzing and managing online marketplaces.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 31, 2018
    Assignee: OATH INC.
    Inventors: Tarun Bhatia, Prasad Chalasani, Rohit Chandra
  • Patent number: 10014866
    Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: July 3, 2018
    Assignee: Invecas, Inc.
    Inventors: Narasimhan Vasudevan, Venkata N. S. N. Rao, Prasad Chalasani
  • Patent number: 9971975
    Abstract: An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 15, 2018
    Assignee: Invecas, Inc.
    Inventors: Venkata N. S. N. Rao, Ravindra Kantamani, Prasad Chalasani
  • Patent number: 9954538
    Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 24, 2018
    Assignee: Invecas, Inc.
    Inventors: Narasimhan Vasudevan, Venkata N. S. N. Rao, Prasad Chalasani
  • Patent number: 9948310
    Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: April 17, 2018
    Assignee: SoCtronics, Inc.
    Inventors: Prasad Chalasani, Venkata N. S. N. Rao
  • Publication number: 20180040032
    Abstract: A digital ad-buying platform uses counterfactual-based incrementality measurement by implementing randomization and/or a correction for auction win bias to avoid the need to identify counterfactual winner types in the control group. This approach can estimate impact at the individual consumer level. Confidence levels can be determined using Gibbs sampling in the context of causal analysis in the presence of non-compliance.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 8, 2018
    Inventors: Prasad Chalasani, Ari Buchalter, Ezra Winston, Jaynth Thiagarajan
  • Publication number: 20180006656
    Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Narasimhan Vasudevan, Venkata N.S.N. Rao, Prasad Chalasani
  • Publication number: 20170373696
    Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Narasimhan Vasudevan, Venkata N.S.N. Rao, Prasad Chalasani
  • Publication number: 20170323222
    Abstract: An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.
    Type: Application
    Filed: March 23, 2017
    Publication date: November 9, 2017
    Inventors: Venkata N.S.N. Rao, Ravindra Kantamani, Prasad Chalasani
  • Patent number: 9715907
    Abstract: An optimized method and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 25, 2017
    Assignee: Invecas, Inc.
    Inventors: Venkata N. S. N. Rao, Ravindra Kantamani, Prasad Chalasani
  • Patent number: 9564905
    Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: February 7, 2017
    Assignee: SOCTRONICS, INC.
    Inventors: Prasad Chalasani, Venkata N. S. N. Rao
  • Patent number: 9467149
    Abstract: A distribution network for distributing clock and reset signals across an address macro has circuit blocks having dividers and counters, drivers connected in a balanced tree, and drivers connected in an unbalanced tree. The dividers and counters are synchronized relative to a clock signal. The drivers connected in the balanced tree distribute the clock signal synchronously to the circuit blocks. The drivers connected in the unbalanced tree distribute a reset signal to the circuit blocks. The clock signal is distributed via the balanced tree as a function of the reset signal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 11, 2016
    Assignee: SOCTRONICS, INC.
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao
  • Publication number: 20160246325
    Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.
    Type: Application
    Filed: May 3, 2016
    Publication date: August 25, 2016
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao
  • Patent number: 9349421
    Abstract: A data path interface for transferring data to a memory device, comprising: programmable delay units (“PDUs”), wherein data is received by the interface according to a first clock signal and wherein the PDUs apply delays to the received data; and align blocks, wherein the align blocks select certain ones of the delayed data as a function of the first clock signal and a second clock signal, and wherein the selected certain ones of the delayed data are processed for transmission to the memory device according to the second clock signal.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: May 24, 2016
    Assignee: SOCTRONICS, INC.
    Inventors: Venkata N. S. N. Rao, Prasad Chalasani
  • Publication number: 20160063522
    Abstract: A marketplace diagnostics framework for analyzing and managing online marketplaces.
    Type: Application
    Filed: November 9, 2015
    Publication date: March 3, 2016
    Inventors: Tarun Bhatia, Prasad Chalasani, Rohit Chandra
  • Patent number: 9183564
    Abstract: A marketplace diagnostics framework for analyzing and managing online marketplaces.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 10, 2015
    Assignee: YAHOO! INC.
    Inventors: Tarun Bhatia, Prasad Chalasani, Rohit Chandra
  • Patent number: 9152920
    Abstract: Disclosed herein is system, method and architecture facilitating goal setting and achievement and providing positive social and economic motivators for goal achievement. Progress toward a goal is tracked and a determination may be made based on the progress whether or not to initiate one or more actions to stimulate progress and/or increase the likelihood of success in achieving a goal and/or achieving a milestone in a path of progression toward the goal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 6, 2015
    Assignee: YAHOO! INC.
    Inventors: Tarun Bhatia, Sam Fishman, Prasad Chalasani, Eric Bax
  • Publication number: 20150221350
    Abstract: A data path interface for transferring data to a memory device, comprising: programmable delay units (“PDUs”), wherein data is received by the interface according to a first clock signal and wherein the PDUs apply delays to the received data; and align blocks, wherein the align blocks select certain ones of the delayed data as a function of the first clock signal and a second clock signal, and wherein the selected certain ones of the delayed data are processed for transmission to the memory device according to the second clock signal.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: Kool Chip, Inc.
    Inventors: Venkata N.S.N. Rao, Prasad Chalasani
  • Publication number: 20140317434
    Abstract: A distribution network, comprises: circuit blocks having counters, wherein the counters are synchronized relative to an input signal; drivers connected in a balanced tree for distributing the input signal synchronously to the circuit blocks; and drivers connected in an unbalanced tree for distributing a reset signal to the circuit blocks, wherein the input signal is distributed via the balanced tree as a function of the reset signal.
    Type: Application
    Filed: January 31, 2014
    Publication date: October 23, 2014
    Applicant: Kool Chip, Inc.
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao
  • Publication number: 20140314190
    Abstract: A method for clocking a physical layer (“PHY”) and a controller of a computing device, comprises the steps of: generating a reference clock signal; synchronizing a plurality of clock signals as a function of the reference clock signal; and clocking the controller and the PHY using the plurality of synchronized clock signals.
    Type: Application
    Filed: October 29, 2013
    Publication date: October 23, 2014
    Applicant: Kool Chip, Inc.
    Inventors: Prasad Chalasani, Venkata N.S.N. Rao