Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each pull up of the memory signal and a pre-emphasis on each pull down of the memory signal based on the delayed signal.

Abstract: An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each pull up of the memory signal and a pre-emphasis on each pull down of the memory signal based on the delayed signal.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (a) buffer write signals presented on a data bus connected between a memory channel and a memory controller, (b) buffer read signals presented on the data bus and (c) condition the write signals. The conditioning may be implemented by (i) converting the write signals to a first differential write signal on a first differential write line and a second differential write signal on a second differential write line and (ii) connecting (a) a negative impedance and (b) a combined resistive and capacitive load between the first and second differential write lines. The second circuit may be configured to (a) convert the first and the second differential write signals to a single-ended write signal and (b) present the single-ended write signal to the data bus.

Abstract: A method and apparatus for implementation of PLL minimum frequency via voltage comparison have been described.