Abstract: A system update appliance includes a processor and a memory device with a Content Addressable Storage (CAS) space and a location addressable storage space. The location addressable storage space partitioned into an object storage space and a device storage space. The processor stores a device entry in the device storage space. The device entry is associated with a device external to the system update appliance and includes a component entry for a component of the device. The component operates based on an update. The component entry includes a description of the component and a pointer to a record stored in the CAS space. The processor stores the record in the CAS space. The record is associated with a combination of the component and the first update. The record includes the description, a second pointer to an update repository, and a third pointer to the object storage space.

Abstract: A method and system are directed to protecting hardware IP, particularly of ASIC designs. Programmability is introduced into an ASIC design to increase the difficulty of formulating ASIC designs as Boolean Satisfiability (SAT) problems. Fine-grain redaction of security-critical information from a design is employed by removing high-entropy logic blocks and subsequently inserting programmable components in place of the redacted portion to hide the actual design intent.

Abstract: Embodiments of the present disclosure provide methods, apparatus, and computer program products for generating an insertion netlist for a target circuit configured for inserting a malicious design alteration into the circuit based on a design identifying reference trigger nets. Features are extracted for each net identified in a netlist for the circuit. A set of reference trigger features is generated for each of the reference trigger nets. A net is selected from the netlist for each set of reference trigger features based on a similarity between the features of the net and the set of reference trigger features. The insertion netlist is generated that includes the circuit with the malicious design alteration inserted at each of the selected nets.

Abstract: Embodiments of the present disclosure provide methods, apparatus, and computer program products for generating an insertion netlist for a target circuit configured for inserting a malicious design alteration into the circuit based on a design identifying reference trigger nets. Features are extracted for each net identified in a netlist for the circuit. A set of reference trigger features is generated for each of the reference trigger nets. A net is selected from the netlist for each set of reference trigger features based on a similarity between the features of the net and the set of reference trigger features. The insertion netlist is generated that includes the circuit with the malicious design alteration inserted at each of the selected nets.