Patents by Inventor Premachandran CHIRAYARIKATHUVEEDU

Premachandran CHIRAYARIKATHUVEEDU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031358
    Abstract: A method for forming a sensor with increased overhang to prevent passivation stress fractures is provided. Embodiments include forming a first passivation layer over a dielectric layer patterned over a first top metal layer of a logic region of a sensor and a second top metal layer of an array region of the sensor; planarizing the first passivation layer and the dielectric layer to form a level surface above the first top metal layer and the second top metal layer; etching the dielectric layer to form a pad opening in the array region of the sensor based on a predetermined overhang value, the pad opening exposing a portion of the surface of the second top metal layer; and forming a second passivation layer over the level surface and the pad opening in the array region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 8, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Aarthi Sridharan, Gong Cheng, Premachandran Chirayarikathuveedu, Fahad Mirza, Carole Graas, Sricharan Tubati, Nurul Islam Mohd
  • Publication number: 20190273051
    Abstract: A method for forming a sensor with increased overhang to prevent passivation stress fractures is provided. Embodiments include forming a first passivation layer over a dielectric layer patterned over a first top metal layer of a logic region of a sensor and a second top metal layer of an array region of the sensor; planarizing the first passivation layer and the dielectric layer to form a level surface above the first top metal layer and the second top metal layer; etching the dielectric layer to form a pad opening in the array region of the sensor based on a predetermined overhang value, the pad opening exposing a portion of the surface of the second top metal layer; and forming a second passivation layer over the level surface and the pad opening in the array region.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Inventors: Aarthi SRIDHARAN, Gong CHENG, Premachandran CHIRAYARIKATHUVEEDU, Fahad MIRZA, Carole GRAAS, Sricharan TUBATI, Nurul Islam MOHD
  • Publication number: 20170033061
    Abstract: Methods for creating effective noise reducing structures in an IC device to significantly reduce TSV-induced noise in an IC substrate of the IC device and the resulting device are disclosed. Embodiments include providing a plurality of circuits on an upper surface of an IC substrate; providing an active TSV in proximity to the circuits, wherein the TSV extends through the IC substrate; forming a noise reducing structure connected to a perimeter of a vertical segment of the active TSV; and connecting the noise reducing structure to an electrical ground node in common with the circuits.
    Type: Application
    Filed: July 29, 2015
    Publication date: February 2, 2017
    Inventors: Mohamed RABIE, Premachandran CHIRAYARIKATHUVEEDU
  • Patent number: 9335368
    Abstract: A device and method to control the heating of an IC chip in a wafer form for measuring various parameters associated therewith are provided. Embodiments include a device having a silicon layer with an upper surface, and on a plastic carrier; a plurality of devices in the silicon layer and electrically coupled through the upper surface to a test control system; a through silicon via (TSV) extending into the silicon layer; and a parallel heating structure adjacent to the plurality of devices electrically coupled to the test control system.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luigi Pantisano, Premachandran Chirayarikathuveedu, Rakesh Ranjan, Anil Kumar
  • Publication number: 20160116526
    Abstract: A device and method to control the heating of an IC chip in a wafer form for measuring various parameters associated therewith are provided. Embodiments include a device having a silicon layer with an upper surface, and on a plastic carrier; a plurality of devices in the silicon layer and electrically coupled through the upper surface to a test control system; a through silicon via (TSV) extending into the silicon layer; and a parallel heating structure adjacent to the plurality of devices electrically coupled to the test control system.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 28, 2016
    Inventors: Luigi PANTISANO, Premachandran CHIRAYARIKATHUVEEDU, Rakesh RANJAN, Anil KUMAR
  • Patent number: 9272899
    Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Huamao Lin, Pradeep Yelehanka
  • Publication number: 20150228555
    Abstract: Structures and methods of fabrication are provided with reduced or cancelled stress within the substrate of the structure adjacent to a through-substrate via. The fabrication method(s) includes: forming a structure with a through-substrate via (TSV) having a reduced device keep-out zone (KOZ) adjacent to the through-substrate via, the forming including: providing the through-substrate via within a substrate of the structure; and providing a stress-offset layer above the substrate selected and configured to provide a desired offset stress to reduce stress within the substrate caused by the presence of the through-substrate via within the substrate. In one embodiment, the stress-offset layer provides a desired compressive stress sufficient to reduce or eliminate tensile stress within the substrate due to the presence of the through-substrate via within the substrate.
    Type: Application
    Filed: February 10, 2014
    Publication date: August 13, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mohamed A. RABIE, Premachandran CHIRAYARIKATHUVEEDU, Mahadeva Iyer NATARAJAN
  • Publication number: 20150115453
    Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.
    Type: Application
    Filed: January 7, 2015
    Publication date: April 30, 2015
    Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Huamao LIN, Pradeep YELEHANKA
  • Patent number: 8940616
    Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Huamao Lin, Pradeep Yelehanka
  • Publication number: 20140030847
    Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Huamao LIN, Pradeep YELEHANKA
  • Patent number: 8513767
    Abstract: A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: August 20, 2013
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Rama Krishna Kotlanka, Rakesh Kumar, Premachandran Chirayarikathuveedu Sankarapillai, Pradeep Ramachandramurthy Yelehanka
  • Publication number: 20120241901
    Abstract: A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type.
    Type: Application
    Filed: March 21, 2011
    Publication date: September 27, 2012
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Rama Krishna KOTLANKA, Rakesh KUMAR, Premachandran CHIRAYARIKATHUVEEDU SANKARAPILLAI, Pradeep Ramachandramurthy YELEHANKA