Patents by Inventor Pu-Xian Gao

Pu-Xian Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190314790
    Abstract: A method of making a titanium dioxide nanowire array includes contacting a substrate with a solvent comprising a titanium (III) precursor, an acid, and an oxidant while microwave heating the solvent, thereby forming a hydrogen titanate H2Ti2O5.H2O nanowire array. The hydrogen titanate nanowire array is annealed to form a titanium dioxide nanowire array. The substrate is seeded with titanium dioxide before starting the hydrothermal synthesis of the hydrogen titanate nanowire array. The titanium dioxide nanowire array is loaded with a platinum group metal to form an exhaust gas catalyst. The titanium dioxide nanowire array can be used to catalyze oxidation of combustion exhaust.
    Type: Application
    Filed: June 1, 2018
    Publication date: October 17, 2019
    Inventors: Pu-Xian Gao, Xingxu Lu, Son Hoang
  • Publication number: 20190041370
    Abstract: Materials, methods of making, and methods of using an apparatus for sensing. The apparatus includes an optical sensing platform; and metal oxide based nanowires incorporated into the optical sensing platform.
    Type: Application
    Filed: July 23, 2018
    Publication date: February 7, 2019
    Inventors: Pu-Xian Gao, Paul Ohodnicki
  • Patent number: 9855549
    Abstract: A metal oxide nanorod array structure according to embodiments disclosed herein includes a monolithic substrate having a surface and multiple channels, an interface layer bonded to the surface of the substrate, and a metal oxide nanorod array coupled to the substrate surface via the interface layer. The metal oxide can include ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide. The substrate can include a glass substrate, a plastic substrate, a silicon substrate, a ceramic monolith, and a stainless steel monolith. The ceramic can include cordierite, alumina, tin oxide, and titania. The nanorod array structure can include a perovskite shell, such as a lanthanum-based transition metal oxide, or a metal oxide shell, such as ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide, or a coating of metal particles, such as platinum, gold, palladium, rhodium, and ruthenium, over each metal oxide nanorod.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: January 2, 2018
    Assignee: UNIVERSITY OF CONNECTICUT
    Inventors: Pu-Xian Gao, Yanbing Guo, Zheng Ren
  • Publication number: 20150258531
    Abstract: A method of making a nanotube array structure includes forming a nanorod array template on a substrate, coating a nanotube material over the nanorod array template, forming a coated template, annealing the coated template, and drying the coated template. The method then includes heating the coated template to an elevated temperature, relative to ambient temperature, at a heating rate while flowing a gas mixture including a reducing gas over the substrate at a flow rate, the reducing gas reacting with the nanorod array template and forming a gaseous byproduct and the nanotube array structure in which nanotubes may be substantially aligned with adjacent nanotubes. The nanotube array structure can be used, for example, in sensor, catalyst, transistor, or solar cell applications.
    Type: Application
    Filed: September 13, 2013
    Publication date: September 17, 2015
    Inventors: Pu-Xian Gao, Zhonghua Zhang
  • Publication number: 20140256534
    Abstract: A metal oxide nanorod array structure according to embodiments disclosed herein includes a monolithic substrate having a surface and multiple channels, an interface layer bonded to the surface of the substrate, and a metal oxide nanorod array coupled to the substrate surface via the interface layer. The metal oxide can include ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide. The substrate can include a glass substrate, a plastic substrate, a silicon substrate, a ceramic monolith, and a stainless steel monolith. The ceramic can include cordierite, alumina, tin oxide, and titania. The nanorod array structure can include a perovskite shell, such as a lanthanum-based transition metal oxide, or a metal oxide shell, such as ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide, or a coating of metal particles, such as platinum, gold, palladium, rhodium, and ruthenium, over each metal oxide nanorod.
    Type: Application
    Filed: September 28, 2012
    Publication date: September 11, 2014
    Applicant: University of Connecticut
    Inventors: Pu-Xian Gao, Yanbing Guo, Zhonghua Zhang, Zheng Ren
  • Patent number: 8704210
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 22, 2014
    Assignee: University of Connecticut
    Inventor: Pu-Xian Gao
  • Patent number: 8350252
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 8, 2013
    Assignee: University of Connecticut
    Inventor: Pu-Xian Gao
  • Publication number: 20110180783
    Abstract: A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and nanoelectronics device systems, is disclosed. A linear or nonlinear nanoparticle (nanowire) junction design that allows precise controllability over an electronic device (e.g., a varistor) performance, which is typically difficult for the traditional sintered bulk varistor, is also disclosed. A localized doping and chemical modulation, across junctions allows flexible and tunable design over the nanoscale grain boundary band engineering is further disclosed. Furthermore, a method of operating memory, using electrostatic potential modulated coding and decoding across periodic nanoparticle grain boundary linearly, is also disclosed.
    Type: Application
    Filed: March 13, 2009
    Publication date: July 28, 2011
    Inventor: Pu-Xian Gao
  • Publication number: 20100180950
    Abstract: A method and corresponding system for providing a uniform nanowire array including uniform nanowires composed of at least three elements is presented. An embodiment of the method includes growing an array of two-element nanowires, and thereafter uniformly doping or alloying each two-element nanowire, with respect to each other two-element nanowire, with at least one doping or alloying element through a wet chemical synthesis with a precursor solution, to produce the uniform array of nanowires composed of at least three elements. The two-element nanowire can include Zn and O, and the at least one doping or alloying element can be Mg, Cd, Mn, Cu, Be, Fe, and Co. Applications of the three-element nanowire array include solar cells and light emitting diodes with improved efficiencies over existing technologies.
    Type: Application
    Filed: November 13, 2009
    Publication date: July 22, 2010
    Applicant: University of Connecticut
    Inventors: Pu-Xian Gao, Paresh Shimpi