Patents by Inventor Puneet Kumar
Puneet Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8443118Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: GrantFiled: July 31, 2012Date of Patent: May 14, 2013Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Publication number: 20130053553Abstract: Described herein are methods for synthesizing heterocyclic, 8-membered ring structures. The methods may allow for preparation of highly substituted 8-membered rings. Also disclosed are heterocyclic, 8-membered ring compounds and pharmaceutical compositions comprising the compounds.Type: ApplicationFiled: August 29, 2012Publication date: February 28, 2013Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATIONInventors: Janis Louie, Puneet Kumar
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Publication number: 20130053565Abstract: Described herein are methods for synthesizing substituted 3-piperidone compounds. Notably, substituted 3-piperidones can also be prepared in enantiopure form. The methods may allow for preparation of highly substituted piperidine cores. Also disclosed are 3-piperidone compounds and pharmaceutical compositions comprising the compounds.Type: ApplicationFiled: August 29, 2012Publication date: February 28, 2013Applicant: UNIVERSITY OF UTAH RESEARCH FOUNDATIONInventors: Janis Louie, Puneet Kumar
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Patent number: 8332559Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.Type: GrantFiled: March 7, 2012Date of Patent: December 11, 2012Assignee: Apple Inc.Inventors: Josh P. de Cesare, Ruchi Wadhawan, Michael J. Smith, Puneet Kumar, Bernard J. Semeria
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Publication number: 20120297096Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: ApplicationFiled: July 31, 2012Publication date: November 22, 2012Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Patent number: 8316188Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache. In an embodiment, the prefetch unit is configured to check for a cache hit for a prefetch request by checking a duplicate cache tags.Type: GrantFiled: June 21, 2011Date of Patent: November 20, 2012Assignee: Apple Inc.Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
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Patent number: 8266338Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: GrantFiled: October 19, 2011Date of Patent: September 11, 2012Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Publication number: 20120167107Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.Type: ApplicationFiled: March 7, 2012Publication date: June 28, 2012Inventors: Josh P. de Cesare, Ruchi Wadhawan, Michael J. Smith, Puneet Kumar, Bernard J. Semeria
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Patent number: 8156275Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.Type: GrantFiled: May 13, 2009Date of Patent: April 10, 2012Assignee: Apple Inc.Inventors: Josh P. de Cesare, Ruchi Wadhawan, Michael J. Smith, Puneet Kumar, Bernard J. Semeria
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Publication number: 20120036289Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: ApplicationFiled: October 19, 2011Publication date: February 9, 2012Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Patent number: 8069279Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: GrantFiled: March 5, 2007Date of Patent: November 29, 2011Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Publication number: 20110264864Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.Type: ApplicationFiled: June 21, 2011Publication date: October 27, 2011Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
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Patent number: 7996624Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.Type: GrantFiled: July 6, 2010Date of Patent: August 9, 2011Assignee: Apple Inc.Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
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Publication number: 20100293401Abstract: In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.Type: ApplicationFiled: May 13, 2009Publication date: November 18, 2010Inventors: Josh P. de Cesare, Ruchi Wadhawan, Michael J. Smith, Puneet Kumar, Bernard J. Semeria
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Publication number: 20100268894Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.Type: ApplicationFiled: July 6, 2010Publication date: October 21, 2010Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
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Patent number: 7783515Abstract: Embodiments of the present invention are directed to apparatuses, systems, methods, and computer program products for: (1) receiving transaction data from a transaction involving a consumer, where the transaction data comprises product-level information; (2) storing the transaction data in memory; and/or (3) posting the transaction data to an account accessible to the consumer.Type: GrantFiled: March 27, 2009Date of Patent: August 24, 2010Assignee: Bank of America CorporationInventors: Puneet Kumar, Debashis Ghosh, Matthew Brian Cincera, Sudeshna Banerjee
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Patent number: 7779208Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.Type: GrantFiled: January 7, 2009Date of Patent: August 17, 2010Assignee: Apple Inc.Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
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Publication number: 20090119488Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.Type: ApplicationFiled: January 7, 2009Publication date: May 7, 2009Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
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Patent number: 7493451Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.Type: GrantFiled: June 15, 2006Date of Patent: February 17, 2009Assignee: P.A. Semi, Inc.Inventors: Sudarshan Kadambi, Puneet Kumar, Po-Yung Chang
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Publication number: 20080222317Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: ApplicationFiled: March 5, 2007Publication date: September 11, 2008Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar