Patents by Inventor Purnendu Sinha

Purnendu Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8464102
    Abstract: A transportation vehicle including a high-resolution clock, an electronic network including two or more tasks, including first and second tasks, and a memory including instructions causing a processor to classify faults in the electronic network using the clock. The steps include receiving a first fault code generated at the first task, receiving a second fault trouble code generated at the second task of the electronic system in response to a second fault, and identifying an execution cycle offset associated with the first and second tasks using an execution schedule, and considering whether the first cycle is separated from the second cycle by the execution cycle offset identified by the schedule. The instructions also cause the processor to identify causal relationships for a plurality of faults via a pair-wise repetition of the above-described analysis for at least one combination of tasks other than the first and second tasks.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: June 11, 2013
    Assignee: GM Global Technology Operations LLC
    Inventors: Purnendu Sinha, Dipankar Das
  • Patent number: 8452465
    Abstract: Systems and methods for reconfiguring ECU tasks for ensuring that a vehicle is operational upon failure of a task or an ECU. A first on-board reconfiguration strategy is generated and executed by an on-board unit of the vehicle to bring the vehicle to a safe state and a second off-line reconfiguration strategy is generated by a remote center unit and then executed by the on-board unit.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: May 28, 2013
    Assignee: GM Global Technology Operations LLC
    Inventors: Purnendu Sinha, Thomas E. Fuhrman
  • Publication number: 20120166878
    Abstract: A transportation vehicle including a high-resolution clock, an electronic network including two or more tasks, including first and second tasks, and a memory including instructions causing a processor to classify faults in the electronic network using the clock. The steps include receiving a first fault code generated at the first task, receiving a second fault trouble code generated at the second task of the electronic system in response to a second fault, and identifying an execution cycle offset associated with the first and second tasks using an execution schedule, and considering whether the first cycle is separated from the second cycle by the execution cycle offset identified by the schedule. The instructions also cause the processor to identify causal relationships for a plurality of faults via a pair-wise repetition of the above-described analysis for at least one combination of tasks other than the first and second tasks.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, LLC
    Inventors: Purnendu Sinha, Dipankar Das
  • Patent number: 8108728
    Abstract: An apparatus and method are provided for analyzing fault tolerance of a system, and performing “what if?” analysis for various fault-tolerant system design options. The fault tolerance analysis approach handles logical failures and quality faults emanating from loss of precision in signal values. The method can detect quality faults, which can allow systems to be built which are resilient to precision losses. Two analysis steps are provided, one static and another simulation-based, which are used in tandem to check the fault tolerance of an automotive or other system. While a simulation-based method checks fault-resilience under specific test cases and fault-scenarios, the static analysis method quickly checks all test cases and fault-scenarios. The static analysis method makes approximations while performing the analysis, and any fault detected is reproduced using the simulation-based method.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: January 31, 2012
    Assignees: GM Global Technology Operations LLC, Indian Institute of Technology Kharagpur
    Inventors: Dipankar Das, Partha P. Chakrabarti, Purnendu Sinha
  • Publication number: 20110246831
    Abstract: An apparatus and method are provided for analyzing fault tolerance of a system, and performing “what if?” analysis for various fault-tolerant system design options. The fault tolerance analysis approach handles logical failures and quality faults emanating from loss of precision in signal values. The method can detect quality faults, which can allow systems to be built which are resilient to precision losses. Two analysis steps are provided, one static and another simulation-based, which are used in tandem to check the fault tolerance of an automotive or other system. While a simulation-based method checks fault-resilience under specific test cases and fault-scenarios, the static analysis method quickly checks all test cases and fault-scenarios. The static analysis method makes approximations while performing the analysis, and any fault detected is reproduced using the simulation-based method.
    Type: Application
    Filed: April 2, 2010
    Publication date: October 6, 2011
    Applicant: GM GLOBAL TECHNOLOGY OPERTIONS, INC.
    Inventors: Dipankar Das, Partha P. Chakrabarti, Purnendu Sinha