Patents by Inventor Qi-De Qian

Qi-De Qian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210073455
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Enhanced physical design tools are provided to read and process anisotropic design rules.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Applicant: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Patent number: 10860773
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 8, 2020
    Assignee: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Patent number: 10846454
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 24, 2020
    Assignee: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Patent number: 10216890
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 26, 2019
    Assignee: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Publication number: 20180181698
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Applicant: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Publication number: 20180181697
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Applicant: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Publication number: 20180181699
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Applicant: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Publication number: 20180011963
    Abstract: An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 11, 2018
    Applicant: IYM TECHNOLOGIES LLC
    Inventor: Qi-De Qian
  • Patent number: 9798853
    Abstract: An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 24, 2017
    Assignee: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Patent number: 9697317
    Abstract: An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 4, 2017
    Assignee: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Publication number: 20160371424
    Abstract: An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 22, 2016
    Inventor: Qi-De Qian
  • Patent number: 8959471
    Abstract: A method and system for improving the yield of integrated devices is invented by adaptively selecting contact and via sizes. According to this invention, the drawn size of via holes in a design layout is selected based on its neighboring layout geometries. The invention comprises identifying the minimal space required for placing a via; analyzing available free space for potential via size increase; identifying the proximity configuration of the via with other vias on the via layer; selecting an appropriate via size based on the free space and proximity configuration to create an improved design layout; and fabricate the new layout with model based proximity correction such that vias of a plurality of sizes are reproduced on silicon within predetermined tolerances.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: February 17, 2015
    Assignee: Qi-De Qtan
    Inventor: Qi-De Qian
  • Patent number: 8464187
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: June 11, 2013
    Inventor: Qi-De Qian
  • Patent number: 8266557
    Abstract: In accordance with the present method and system for anisotropic integrated circuit layout we extract a set of anisotropic design rules for integrated circuit manufacturing systems that have directional preference. We enhance various physical design tools to read and process anisotropic design rules in order to generate anisotropic design layout that takes advantage of an anisotropic manufacturing system.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: September 11, 2012
    Inventor: Qi-De Qian
  • Patent number: 8176445
    Abstract: We disclose a method for optimizing integrated circuit layout which comprises analyzing constraint relationship among objects in an initial layout; constructing local modifications to the constraint relationship; forming new constraint relationships by combining initial constraint relationships with their local modifications; and producing a new layout by implementing the new constraint relationships. Local modification to constraints provides a framework for bringing detailed local information into the design process in a highly automated manner, which can be applied to a wide range of situations. We disclose preferred embodiments on improving lithography printability, reducing defect susceptibility, and improving circuit performance such as reducing layout variability and leakage.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: May 8, 2012
    Inventor: Qi-De Qian
  • Publication number: 20100162194
    Abstract: A method and system for improving the yield of integrated devices is invented by adaptively selecting contact and via sizes. According to this invention, the drawn size of via holes in a design layout is selected based on its neighboring layout geometries. The invention comprises identifying the minimal space required for placing a via; analyzing available free space for potential via size increase; identifying the proximity configuration of the via with other vias on the via layer; selecting an appropriate via size based on the free space and proximity configuration to create an improved design layout; and fabricate the new layout with model based proximity correction such that vias of a plurality of sizes are reproduced on silicon within predetermined tolerances.
    Type: Application
    Filed: February 17, 2010
    Publication date: June 24, 2010
    Inventor: Qi-De Qian
  • Patent number: 7698676
    Abstract: A method and system for improving the yield of integrated devices by adaptively selecting contact and via sizes is described. According to this invention, the drawn size of via holes in a design layout is selected based on its adjacent geometry objects. The invention comprises identifying the minimal space required for placing a via; analyzing available free space for potential via size increase; identifying the proximity configuration of the via with other vias; selecting an appropriate via size based on the free space and proximity configuration to create a new design layout; and fabricate the new layout with proximity correction on the photomask such that vias of a plurality of sizes are reproduced on silicon within predetermined tolerances.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: April 13, 2010
    Inventor: Qi-De Qian
  • Patent number: 7448012
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: November 4, 2008
    Inventor: Qi-De Qian
  • Patent number: 7043071
    Abstract: Masks that include optical proximity correction or phase shifting regions are increasingly being used in the manufacturing process. These masks, either initially or after repair, can have “soft” defects, e.g. phase and/or transmission defects. In accordance with one feature of the invention, soft defect information can be computed from standard test images of a mask. This soft defect information can be used to generate an accurate simulated wafer image, thereby providing valuable defect impact information to a user. Knowing the impact of the soft defect can enable a user to make better decisions regarding the mask. Specifically, a user can now with confidence accept the mask for the desired lithographic process, repair the mask at certain critical locations, or reject the mask, all without exposing a wafer.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: May 9, 2006
    Assignee: Synopsys, Inc.
    Inventors: Qi-De Qian, Linyong Pang
  • Publication number: 20040052411
    Abstract: Masks that include optical proximity correction or phase shifting regions are increasingly being used in the manufacturing process. These masks, either initially or after repair, can have “soft” defects, e.g. phase and/or transmission defects. In accordance with one feature of the invention, soft defect information can be computed from standard test images of a mask. This soft defect information can be used to generate an accurate simulated wafer image, thereby providing valuable defect impact information to a user. Knowing the impact of the soft defect can enable a user to make better decisions regarding the mask. Specifically, a user can now with confidence accept the mask for the desired lithographic process, repair the mask at certain critical locations, or reject the mask, all without exposing a wafer.
    Type: Application
    Filed: September 13, 2002
    Publication date: March 18, 2004
    Applicant: Numerical Technologies, Inc.
    Inventors: Qi-De Qian, Linyong Pang