Abstract: A power supply management device includes an internal power supply circuit, switches, a comparator circuit, and a control circuit. The internal power supply circuit is configured to output a first supply voltage to a node. The switches are coupled between the node and a plurality of first circuits. The comparator circuit is configured to compare a voltage on the node with a reference voltage when the node does not receive the first supply voltage to generate a flag signal. The control circuit is configured to determine whether the node receives a second supply voltage from an external power supply circuit according to the flag signal. If the node receives the second supply voltage, the control circuit is further configured to turn off the internal power supply circuit and gradually turn on the switches, in order to provide the second supply voltage to the first circuits via the switches.

Abstract: A power supply management device includes an internal power supply circuit, switches, a comparator circuit, and a control circuit. The internal power supply circuit is configured to output a first supply voltage to a node. The switches are coupled between the node and a plurality of first circuits. The comparator circuit is configured to compare a voltage on the node with a reference voltage when the node does not receive the first supply voltage to generate a flag signal. The control circuit is configured to determine whether the node receives a second supply voltage from an external power supply circuit according to the flag signal. If the node receives the second supply voltage, the control circuit is further configured to turn off the internal power supply circuit and gradually turn on the switches, in order to provide the second supply voltage to the first circuits via the switches.

Abstract: An integrated circuit with self-reference impedance includes an input/output pin provided for connection to an external impedance, a local impedance, a reference power circuit, a switching circuit, and a control circuit. The switching circuit is configured to conduct a connection between the input/output pin and the reference power circuit in a first state and to conduct a connection between the local impedance and the reference power circuit in a second state. The control circuit is configured to detect whether the external impedance is connected to the input/output pin or not and to generate a detection signal. The control circuit controls the switching circuit into the first state or the second state according to the detection signal. In the first state, the reference power circuit generates a reference signal according to the external impedance. In the second state, the reference power circuit generates the reference signal according to the local impedance.

Abstract: The present disclosure discloses a multi-path image processing apparatus. An image merging circuit is configured to receive image frames that at least one of the image frames has a largest row number, generate redundant pixel row for each of the image frames that has a row number smaller than the largest row number such that the row number of each of the image frames equals to the largest row number, generate redundant pixel columns for each of the image frames having the number thereof determined by a size of a largest operation window, and merge each two of the image frames through the redundant columns thereof to generate a merged image frame. An image processing circuit performs image processing procedure on the merged image frame to generate a processed merged image frame, wherein at least a part of the image processing procedure is operated according to the largest operation window. An image segmentation circuit segments the processed merged image frame to generate processed image frames.

Abstract: The present disclosure discloses a multi-path image processing apparatus. An image merging circuit is configured to receive image frames that at least one of the image frames has a largest row number, generate redundant pixel row for each of the image frames that has a row number smaller than the largest row number such that the row number of each of the image frames equals to the largest row number, generate redundant pixel columns for each of the image frames having the number thereof determined by a size of a largest operation window, and merge each two of the image frames through the redundant columns thereof to generate a merged image frame. An image processing circuit performs image processing procedure on the merged image frame to generate a processed merged image frame, wherein at least a part of the image processing procedure is operated according to the largest operation window. An image segmentation circuit segments the processed merged image frame to generate processed image frames.