Abstract: A sterilization structure, a sterilization board, and a display device are disclosed. The sterilization structure includes an active layer, wherein, one surface of the active layer has an exposed region, and a material of the active layer includes a laser-induced graphene material.

Abstract: This disclosure discloses an array substrate, and a production method, a display panel, and a display apparatus thereof. Particularly, this disclosure proposes a method of producing an array substrate, having the following steps: providing a substrate having a drive transistor region and a switch transistor region thereon; forming an preset layer for active layer on a side of the substrate; patterning the preset layer for active layer to form a drive active layer and a switch active layer, wherein an orthographic projection of the drive active layer on the substrate is located in the drive transistor region, an orthographic projection of the switch active layer on the substrate is located in the switch transistor region, and a carrier concentration in the drive active layer is less than a carrier concentration in the switch active layer.

Abstract: Disclosed are an array substrate, a method for fabricating the same, a display panel, and a display device, and the array substrate includes: an underlying substrate, and gate lines and data lines located on the underlying substrate, and intersecting with each other, a layer where the gate lines are located is between a layer where the data lines are located, and the underlying substrate; and the array substrate further includes a buffer layer located between the underlying substrate and the layer where the gate lines are located; and the buffer layer includes a plurality of through-holes, where orthographical projections of the through-holes onto the underlying substrate cover orthographical projections of the areas where the gate lines intersect with the data lines, onto the underlying substrate.

Abstract: A thin film transistor, including: at least one active layer pattern including a first conductive pattern, a second conductive pattern, and a semiconductor pattern; a gate on a side of the active layer pattern; a first electrode and a second electrode on a side of the gate away from the active layer pattern, and respectively electrically connected with the first conductive pattern and the second conductive pattern, a conductive shielding pattern is provided corresponding to the semiconductor pattern in at least one active layer pattern, the conductive shielding pattern is on a side of the semiconductor pattern away from the gate and is electrically connected with the first electrode, and a buffer layer is between the conductive shielding pattern and the semiconductor pattern; an orthographic projection of the conductive shielding pattern on a plane where the semiconductor pattern corresponding thereto is located at least partially covers the semiconductor pattern corresponding.

Abstract: A capacitor, an array substrate and a method for manufacturing the same, and a display panel are provided. The capacitor includes a main body including a first pole plate and a second pole plate disposed opposite to each other, and the capacitor further includes at least one auxiliary body. Any one of the at least one auxiliary body includes a third pole plate and a fourth pole plate disposed opposite to each other, and neither the third pole plate nor the fourth pole plate extends in a plane where the first pole plate is located or a plane where the second pole plate is located. The main body is connected in parallel with the at least one auxiliary body. The array substrate includes a transistor and the capacitor provided by the present disclosure, and the transistor is electrically connected to the capacitor.

Abstract: The present invention relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a first electrode layer. The first electrode layer may include an indium tin oxide layer and a planarization layer. The indium tin oxide layer is disposed on a substrate and includes indium tin oxide particles; the planarization layer is disposed on a side of the indium tin oxide layer away from the substrate, and fills at least part of gaps between the indium tin oxide particles, and the planarization layer can conduct electricity.

Abstract: Embodiments of the present disclosure provide an organic light emitting transistor comprising: a substrate, and a gate electrode, a gate insulating layer, source/drain electrodes and a light emitting functional layer disposed on the substrate, wherein the organic light emitting transistor further comprises an external electrode coupled to the gate electrode in series, wherein a temperature-dependent resistance change rate of the gate electrode is different from a temperature-dependent resistance change rate of the external electrode.

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof, and a display device including the array substrate. The array substrate includes a substrate, a first electrode on the substrate, a light-emitting layer on a side of the first electrode away from the substrate, a second electrode on a side of the light-emitting layer away from the first electrode, and an auxiliary electrode on the side of the light-emitting layer away from the first electrode and electrically connected with the second electrode.

Abstract: Provided are a display substrate and a display apparatus. The display substrate includes a base substrate, and an auxiliary cathode structure located on a side of the base substrate, the auxiliary cathode structure including a first conductive layer, an intermediate support layer, and a second conductive layer. In an implementation, a side of the intermediate support layer close to the first conductive layer includes any one or more of first protrusions and first grooves, and a side of the first conductive layer close to the intermediate support layer includes any one or more of second grooves engaged with the first protrusions and second protrusions engaged with the first grooves which are correspondingly disposed.

Abstract: An array substrate includes an insulation layer and one or more stepped holes each penetrating through the insulation layer in a direction perpendicular to the insulation layer. Each stepped hole includes a first hole and a second hole under the first hole, a radius of the first hole at a bottom is a first radius, a radius of the second hole at a top is a second radius which is substantially smaller than the first radius, and a difference between the first radius and the second radius is 0.2 ?m to 0.6 ?m.

Abstract: The disclosure relates to a thin film transistor. The thin film transistor may include a substrate, an active layer on the substrate, a gate on the active layer, and a source and a drain. The active layer may include a first conducting region, a second conducting region, and a channel region between the first conducting region and the second conducting region. An orthographic projection of the source and an orthographic projection of the drain on the substrate may cover at least an orthographic projection of a first conducting region and an orthographic projection of a second conducting region on the substrate.

Abstract: The present disclosure is related to a thin film transistor. The thin film transistor may include an active layer; a gate insulating layer on the active layer; and a gate and a plurality of metal films on the gate insulating layer. The plurality of metal films may be spaced apart from the gate, and insulated from the gate and the active layer.

Abstract: The disclosure discloses an array substrate and a preparation method thereof, a display panel and a display device. The array substrate includes: a substrate, and a first metal layer, a metal oxide layer and a second metal layer which are sequentially stacked and isolated from each other on the substrate; the first metal layer includes a light shading metal, a first electrode, and an anti-static line; the metal oxide layer includes a first active layer; the second metal layer includes a gate line and a second electrode; the gate line is connected with the anti-static line through a first TFT, one of the first electrode and the second electrode forms the source and drain electrodes of the first TFT, and the other forms the gate electrode of the first TFT; and the source is electrically connected with the gate line, and the drain is electrically connected with the anti-static line.

Abstract: A display panel having a pixel region includes a base substrate, a plurality of pixel circuits located in the pixel region, and a plurality of light-emitting structures located in the pixel region. Each pixel circuit includes a storage capacitor and a plurality of transistors. The light-emitting structures are configured to emit light of at least three primary colors. Each light-emitting structure includes a light-emitting device. Each pixel circuit is coupled to the light-emitting device in a corresponding light-emitting structure, and a surface of the light-emitting device proximate to the base substrate is a light exit surface. Among the light-emitting structures, an orthogonal projection of an effective light-emitting region, on the base substrate, of the light-emitting device in a first light-emitting structure with a shortest light-emitting wavelength, is spaced apart from orthogonal projections of all storage capacitors of the plurality of pixel circuits on the base substrate.

Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The thin film transistor is formed on a substrate and includes: an active layer on the substrate, the active layer including a source region, a drain region, and a channel region between the source region and the drain region; a first gate electrode on a side of the active layer away from the substrate; and a second gate electrode on a side of the first gate electrode away from the substrate, wherein a thickness of the first gate electrode is smaller than a thickness of the second gate electrode.

Abstract: A display substrate, a preparation method thereof, and a display apparatus are provide. The display substrate includes: a base substrate, an active layer disposed on the base substrate, a first gate insulating layer disposed on the active layer, a first conductive layer disposed on the first gate insulating layer, and a second conductive layer disposed on the first conductive layer and electrically connected with the first conductive layer; an orthographic projection of the first conductive layer on the base substrate does not overlap with an orthographic projection of the active layer on the base substrate; the second conductive layer includes gates; orthographic projections of the gates on the base substrate and the orthographic projection of the active layer on the base substrate have an overlap area; and the display substrate further includes: at least one insulating layer located between the first conductive layer and the gates.

Abstract: A thin film transistor, a display panel and a preparation method thereof and a display apparatus are provided. The thin film transistor includes: a substrate; a gate metal located on a side of the substrate; a gate insulating layer located on a side of the gate metal away from the substrate; an active layer located on a side of the gate insulating layer away from the substrate; a first metal oxide and a second metal oxide which are located on a side of the active layer away from the substrate and are arranged on a same layer; and a source metal and a drain metal which are located on sides of the first metal oxide and the second metal oxide away from the substrate and are arranged in a same layer.

Abstract: A display panel and a fabricating method thereof, and a displaying device. The display panel includes a substrate, a resistance reducing trace, an inter-layer-medium layer and a signal line. The substrate is divided into a plurality of sub-pixel regions and a pixel separating region. The resistance reducing trace is provided on the pixel separating region of the substrate. The inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace. The signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.

Abstract: Provided are a detection method and a detection device, the detection method includes: in a first writing stage, providing an active voltage to each data line, each power supply terminal, both ends of a first gate line to-be-detected, an absolute value of the active voltage of each data line is smaller than that of the active voltage of the power supply terminal, an absolute value of the active voltage of the first gate line to-be-detected is smaller than that of the active voltage of each data line; in a first detection stage, maintaining the active voltage of the power supply terminal, providing an inactive voltage to the first gate line to-be-detected and providing an active voltage to the data line, detecting voltages at second electrodes of storage capacitors corresponding to the first gate line to-be-detected, determining whether the first gate line to-be-detected has breakpoint according to the detected voltages.

Abstract: A pressure sensing unit includes: a first substrate and a second substrate opposite to each other; and at least one vertical thin film transistor disposed between the first substrate and the second substrate. Each vertical thin film transistor includes a first electrode, a semiconductor active layer, a second electrode, at least one insulating support, and a gate electrode sequentially disposed in a direction extending from the first substrate to the second substrate. A first air gap is formed by the presence of the at least one insulating support between the gate electrode and the second electrode of each vertical thin film transistor.