Patents by Inventor Qingjiang Ma

Qingjiang Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10929318
    Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module, wherein the memory module comprises one or more memory groups each having a plurality of memory blocks, and the memory controller comprising: a registering clock driver coupled to the memory module for providing to the memory module a data access command so as to control access to the memory module; one or more data buffers coupled to the registering clock driver, and each data buffer coupled to a memory group via a memory group data interface; wherein at least one of the memory group data interfaces comprises a plurality of data buses each coupled to one or more memory blocks of the memory group that the memory group data interface coupled to, such that the memory group can exchange data with the data buffer via the plurality of data buses under the control of the registering clock driver.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 23, 2021
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Qingjiang Ma, Gang Shan, Chunyi Li
  • Publication number: 20200293467
    Abstract: The application discloses a memory controller coupled to a memory module for controlling access to the memory module, wherein the memory module comprises one or more memory groups each having a plurality of memory blocks, and the memory controller comprising: a registering clock driver coupled to the memory module for providing to the memory module a data access command so as to control access to the memory module; one or more data buffers coupled to the registering clock driver, and each data buffer coupled to a memory group via a memory group data interface; wherein at least one of the memory group data interfaces comprises a plurality of data buses each coupled to one or more memory blocks of the memory group that the memory group data interface coupled to, such that the memory group can exchange data with the data buffer via the plurality of data buses under the control of the registering clock driver.
    Type: Application
    Filed: December 20, 2019
    Publication date: September 17, 2020
    Inventors: Qingjiang MA, Gang SHAN, Chunyi LI
  • Publication number: 20160299719
    Abstract: The application discloses a memory device. The memory device has a volatile memory module and a non-volatile memory module. The memory device receives a data access command from an external module through a memory interface and exchanges data with the external module accordingly. An access control module is coupled to the memory interface to receive the data access command. A non-volatile memory controller is coupled to the non-volatile memory module. The non-volatile memory module receives the data access command and exchanges data with the non-volatile memory module accordingly. A data buffering module is coupled to the volatile memory module, the non-volatile memory controller and the memory interface. The data buffering module is also coupled to the access controller module to receive the data access command. The data buffering module provides the data access command to the non-volatile memory controller to exchange data with the non-volatile memory controller according to the data access command.
    Type: Application
    Filed: December 2, 2015
    Publication date: October 13, 2016
    Inventors: Jie Liu, Qingjiang Ma
  • Patent number: 9201817
    Abstract: The present invention relates to a method for allocating addresses to data buffers in a distributed buffer chipset, in which a memory controller informs a central buffer of the beginning of address allocation through a Command/Address channel (CA), and then the central buffer informs through a data control channel all the data buffers of preparing for receiving address parameters through respective data channels, and in this way, each data buffer receives and latches the respective address parameter from the memory controller through the respective data, thus avoiding the defect in the prior art that the size of the data buffer and the size of the entire distributed buffer chipset is bigger as several address pins need to be additionally configured in each data buffer to allocate the respective address parameter.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 1, 2015
    Assignee: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventors: Huaixiang Chu, Qingjiang Ma
  • Patent number: 9104533
    Abstract: A voltage and timing calibration method used in a memory system. A memory controller adjusts timing and voltages of the controller and voltages of a memory buffer according to data returned by the buffer based on timing and voltages at a memory controller side of the buffer, to calibrate timing and voltages between the controller and controller side. According to data read by the buffer from a memory chip unit on the basis of timing and voltages at a memory chip side of the buffer, the controller adjusts the timing and voltage at the chip side and the voltage of the chip unit; or the buffer adjusts the timing and voltage at the chip side and the voltage of the chip unit, to calibrate the timing and voltage between the chip side and chip unit. Therefore, hardware resources of the buffer can be saved and the circuit can be simplified.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 11, 2015
    Assignee: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventors: Chunyi Li, Qingjiang Ma
  • Patent number: 9026726
    Abstract: The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data output circuit, and a data receiving circuit. The memory module includes a memory buffer and at least two memory chips. The memory buffer includes a second control circuit, a write circuit, and a read circuit. The advantage of the present invention is that, when data is read or written into the memory chip, especially a DDR4 X4 memory chip, low power consumption of interface data transmission can be achieved through a data bus inversion control line DBI.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: May 5, 2015
    Assignee: Montage Technology (Shanghai) Co., Ltd.
    Inventors: Haiyang Li, Qingjiang Ma
  • Patent number: 9003154
    Abstract: A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 7, 2015
    Assignee: Montage Technology (Shanghai) Co., Ltd.
    Inventors: Chunyi Li, Qingjiang Ma
  • Patent number: 8843801
    Abstract: The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: September 23, 2014
    Assignee: Montage Technology (Shanghai) Co., Ltd.
    Inventors: Qingjiang Ma, Haiyang Li
  • Publication number: 20130132660
    Abstract: The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data output circuit, and a data receiving circuit. The memory module includes a memory buffer and at least two memory chips. The memory buffer includes a second control circuit, a write circuit, and a read circuit. The advantage of the present invention is that, when data is read or written into the memory chip, especially a DDR4 X4 memory chip, low power consumption of interface data transmission can be achieved through a data bus inversion control line DBI.
    Type: Application
    Filed: August 9, 2011
    Publication date: May 23, 2013
    Applicant: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventors: Haiyang Li, Qingjiang Ma
  • Publication number: 20130124816
    Abstract: A device requiring address allocation, a device system, and an address allocation method. A control device in the device system transmits currently allocated address information and a contention start signal to each device requiring address allocation in the device system through a bus, and the devices requiring address allocation with address allocation flag information being that no address information is allocated output an address contention signal. When outputting the address contention signal, each device requiring address allocation determines whether the currently allocated address information is available according to whether the other devices requiring address allocation with address allocation flag information being that no address information is allocated already output address contention signals.
    Type: Application
    Filed: August 15, 2012
    Publication date: May 16, 2013
    Applicant: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventors: Chunyi LI, Qingjiang MA
  • Publication number: 20130093459
    Abstract: A termination device system is provided that includes a device required to be terminated with a resistor and a termination circuit. The termination circuit includes a termination resistor circuit and a judgment circuit connected to the termination resistor circuit. The termination resistor circuit includes at least one controlled termination unit. Each controlled termination unit includes a termination connecting end for connecting the device required to be terminated with a resistor, a controlled switch and a resistor, and provides, based on on/off of the controlled switch, a termination resistor for the device connected to the termination connecting end. The judgment circuit judges whether the device is required to be connected to the termination resistor based on a control instruction of a control device controlling the device connected to the termination connecting end, to output an on/off control signal to the controlled switch of the termination resistor circuit to control on/off.
    Type: Application
    Filed: August 31, 2012
    Publication date: April 18, 2013
    Applicant: MONTAGE TECHNOLOGY (SHANGHAI) CO. LTD.
    Inventors: Chunyi LI, Qingjiang MA
  • Publication number: 20130046941
    Abstract: The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer. Advantages of the present invention lie in that: data can be transmitted with a memory controller in a low power consumption manner, and the data transmitted based on conversion control data can be read out of or written into a DDR4 memory chip.
    Type: Application
    Filed: August 8, 2011
    Publication date: February 21, 2013
    Applicant: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
    Inventors: Qingjiang Ma, Haiyang Li
  • Publication number: 20130036287
    Abstract: The present invention relates to a method for allocating addresses to data buffers in a distributed buffer chipset, in which a memory controller informs a central buffer of the beginning of address allocation through a Command/Address channel (CA), and then the central buffer informs through a data control channel all the data buffers of preparing for receiving address parameters through respective data channels, and in this way, each data buffer receives and latches the respective address parameter from the memory controller through the respective data, thus avoiding the defect in the prior art that the size of the data buffer and the size of the entire distributed buffer chipset is bigger as several address pins need to be additionally configured in each data buffer to allocate the respective address parameter.
    Type: Application
    Filed: October 18, 2011
    Publication date: February 7, 2013
    Applicant: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD
    Inventors: Huaixiang Chu, Qingjiang Ma
  • Patent number: 7864906
    Abstract: A system (101) for clock signal synchronization includes a data analyzer (104) and a synchronized clock signal generator (105) coupled to an RC oscillator (103). The data analyzer (104) generates a digital control signal representing the number of cycles of a reference signal of the RC oscillator (103) during an eight-bit period of an incoming token packet. The synchronized signal clock generator (105) uses the digital control signal to lock a clock signal to packets that have the same bit rate as the token packet.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: January 4, 2011
    Assignee: Apexone Microelectronics Ltd.
    Inventors: Qingjiang Ma, James Y. Gao, Yongqing Ren
  • Publication number: 20070159221
    Abstract: A system (101) for clock signal synchronization includes a data analyzer (104) and a synchronized clock signal generator (105) coupled to an RC oscillator (103). The data analyzer (104) generates a digital control signal representing the number of cycles of a reference signal of the RC oscillator (103) during an eight-bit period of an incoming token packet. The synchronized signal clock generator (105) uses the digital control signal to lock a clock signal to packets that have the same bit rate as the token packet.
    Type: Application
    Filed: December 13, 2004
    Publication date: July 12, 2007
    Inventors: Qingjiang Ma, James Gao, Yongqing Ren
  • Patent number: D938621
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 14, 2021
    Assignee: NINGBO HELONG NEW MATERIAL CO., LTD
    Inventors: Qingjiang Ma, Zhiping Xu, Bing Zhang, Yun Zhou, Panpan Zhou
  • Patent number: D938622
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 14, 2021
    Assignee: NINGBO HELONG NEW MATERIAL CO., LTD
    Inventors: Qingjiang Ma, Zhiping Xu, Bing Zhang, Yun Zhou, Panpan Zhou
  • Patent number: D938623
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 14, 2021
    Assignee: NINGBO HELONG NEW MATERIAL CO., LTD
    Inventors: Qingjiang Ma, Zhiping Xu, Bing Zhang, Yun Zhou, Panpan Zhou
  • Patent number: D938624
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: December 14, 2021
    Assignee: NINGBO HELONG NEW MATERIAL CO., LTD
    Inventors: Qingjiang Ma, Zhiping Xu, Bing Zhang, Yun Zhou