Abstract: The present application discloses a method for manufacturing a full silicide metal gate bulk silicon multi-gate fin field effect transistor, which comprises the steps of: forming at least one fin on the semiconductor substrate; forming a gate stack structure on top and side surfaces of the fin; forming a source/drain extension area in the fin on both sides of the gate stack structure; forming a source/drain area on both sides of the source/drain extension area; forming silicide on the source/drain area; forming a full silicide metal gate electrode; and forming contact and implementing metalization. The present invention eliminates the self-heating effect and the floating body effect of SOI devices, then has a much lower cost, overcomes such defects as the polysilicon gate depletion effect, Boron penetration effect, and large series resistance of polysilicon gate electrodes, and has good compatibility with the planar COMS technology, thus it can be easily integrated.

Abstract: A method for manufacturing a multigate device is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form a protruding fin; etching the semiconductor substrate at the bottom of the fin so as to form a gap between the fin and the semiconductor substrate; forming a dielectric layer which covers the semiconductor substrate and the fin and fills the gap; and etching the dielectric layer so as to expose the top and a portion of sidewalls of the fin. The present invention can realize isolation between fins with a simple process, which costs relatively low and is suitable for massive industrial application.

Abstract: A method for integrating a replacement gate in a semiconductor device is disclosed.

Abstract: The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs.

Abstract: A method of patterning a dielectric layer with a Zep 520 positive EB photoresist as a mask, comprising the steps of depositing an ?-Si film on the dielectric layer; providing a layer of Zep 520 positive EB photoresist having high-resolution patterns therein by electron beam direct writing; etching the ?-Si film by chlorine-based plasma with the layer of Zep 520 positive EB photoresist as a mask, so as to transfer the high-resolution patterns of the Zep 520 positive EB photoresist to the underlying ?-Si film; removing the Zep 520 positive EB photoresist; etching the dielectric layer by fluorine-based plasma with the ?-Si film having high-fidelity patterns as a hard mask, so as to provide patterns of recesses; and removing the ?-Si film by wet etching or dry etching. The inventive method is completely compatible with and easily incorporated into the conventional CMOS processes, with high reliability and resolution for providing nanoscale fine patterns of recesses.

Abstract: The present invention provides a method for removing polymer after etching a gate stack structure of high-K gate dielectric/metal gate. The method mainly comprises the following steps: 1): forming a gate stack structure of interface Si2/high-K gate dielectric/metal gate/poly-silicon/hard mask in sequence on a silicon substrate with device isolations formed thereon; 2): forming a resist pattern by the lithography; 3): etching the gate stack structure; and 4): immersing the resultant structure of the step 3) in an etching solution to remove the polymer, wherein the etching solution consists of HF, HCl and water, the ratio of HF by volume is 0.2˜1% and the ratio of HCl by volume is 5˜15%.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

Abstract: The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or oxynitride layer on a semiconductor substrate by rapid thermal oxidation or chemical method after conventional LOCOS or STI dielectric isolation is completed; depositing high-K gate dielectric and performing rapid thermal annealing; depositing a composite metal gate; depositing a barrier metal layer; depositing a polysilicon film and a hard mask and then performing photolithography and etching the hard mask; removing photoresist and etching the polysilicon film, the barrier metal layer, the metal gate, the high-K gate dielectric, and the interface oxide layer in sequence to form a gate stack structure of polysilicon film/barrier metal layer/metal gate/high-K gate dielectric; forming spacers, source/drain implantation in a conventional manner and performing rapid thermal annealing, whereby while source/drain dopants ar

Abstract: A method of adjusting a metal gate work function of an NMOS device comprises: depositing a layer of metal nitride film or metal film on a high K dielectric as a metal gate electrode by a physical vapor deposition process; implanting elements such as Tb, Er, Yb or Sr into the metal gate electrode by an ion implantation process; performing a high temperature annealing so that the doped metal ions are driven to and accumulate on the interface between the metal gate electrode and the high K gate dielectric, or form dipoles by an interface reaction on the interface between the high K gate dielectric and SiO2. The method is capable of adjusting the metal gate work function, and is well-compatible with CMOS process.

Abstract: The present invention relates to a semiconductor and a method for manufacturing the same. The semiconductor structure comprises an NMOS device comprising a first gate structure and a PMOS device comprising a second gate structure; a first stress liner, at least formed on both sides of the first gate structure of said NMOS device; a second stress liner, at least formed on both sides of the second gate structure of said PMOS device; wherein said first stress liner is a spin-on glass (SOG) film with tensile stress, said second stress liner is formed of a material that can introduce compressive stress into the channel of the PMOS device. The present invention can reduce the difficulty of the process of manufacturing dual stress liner using the same material, e.g. nitride, and can reduce influence of nitride having a high dielectric constant upon the device interconnect delay while still maintaining the tensile strain advantage.

Abstract: A method for improving the efficiency of the electron-beam exposure is provided, comprising: step 1) coating a positive photoresist on a wafer to be processed, and performing a pre-baking; step 2) separating pattern data, optically exposing a group of relatively large patterns, and then performing a post-baking; step 3) developing the positive photoresist; step 4) performing a plasma fluorination; step 5) performing a baking to solidify the photoresist; step 6) coating a negative electron-beam resist and performing a pre-baking; step 7) electron-beam exposing a group of fine patterns; step 8) performing a post-baking; and step 9) developing the negative electron-beam resist, so that the fabrication of the patterns is finished. According to the invention, it is possible to save 30-60% of the exposure time. Thus, the exposure efficiency is significantly improved, and the cost is greatly reduced. Further, the method is totally compatible with the CMOS processes, without the need of any special equipments.

Abstract: A method of manufacturing a metal gate/high K dielectric gate stack includes the steps of: forming an interfacial layer of SiON or SiO2 on a silicon substrate; depositing a high K dielectric film on the interfacial layer; performing a rapid thermal anneal of the high K dielectric film; depositing a TaN metal gate electrode film on the high K dielectric film; depositing a polysilicon gate layer on the TaN metal gate electrode film, and then depositing a hard mask layer; patterning a photoresist mask, and performing an anisotropic etching of the hard mask layer; removing the photoresist mask, and etching the polysilicon by reactive ion etching with the hard mask as masking layer using a mixed gas of Cl2/HBr; and etching the TaN metal gate electrode/high K dielectric gate stack by reactive ion etching with the hard mask as masking layer using BCl3-based etchant gas.

Abstract: The present application discloses a method for manufacturing a semiconductor device, comprising: forming a local buried isolation dielectric layer in a semiconductor substrate; forming a fin in the semiconductor substrate and on top of the local buried isolation dielectric layer; forming a gate stack structure on a top surface and side surfaces of the fin; forming source/drain structures in portions of the fin which are on opposite sides of the gate stack structure; and performing metallization. A conventional quasi-planar top-down process is utilized in the present invention to achieve a good compatibility with the CMOS planar processes, easy integration, and suppression of short channel effects, which promotes the development of MOSFETs having reduced sizes.

Abstract: The present invention relates to a method of introducing strain into a channel and a device manufactured by using the method, the method comprising: providing a semiconductor substrate; forming a channel in the semiconductor substrate; forming a first gate dielectric layer on the channel; forming a polysilicon gate layer on the first gate dielectric layer; doping or implanting a first element into the polysilicon gate layer; removing a part of the first gate dielectric layer and polysilicon gate layer to thereby form a first gate structure; forming a source/drain extension region in the channel; forming spacers on both sides of the first gate structure; forming a source/drain in the channel; and performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing a first strain in the polysilicon gate layer, and introducing the first strain through the gate dielectric layer to the channel.

Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.

Abstract: The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device (200, 300), comprising a semiconductor substrate (202, 302); a channel formed on the semiconductor substrate (202, 302); a gate dielectric layer (204, 304) formed on the channel; a gate conductor (206, 306) formed on the gate dielectric layer (204, 304); and a source and a drain formed on both sides of the gate; wherein the gate conductor (206, 306) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

Abstract: A method for improving the efficiency of the electron-beam exposure is provided, comprising: step 1) coating a positive photoresist on a wafer to be processed, and performing a pre-baking; step 2) separating pattern data, optically exposing a group of relatively large patterns, and then performing a post-baking; step 3) developing the positive photoresist; step 4) performing a plasma fluorination; step 5) performing a baking to solidify the photoresist; step 6) coating a negative electron-beam resist and performing a pre-baking; step 7) electron-beam exposing a group of fine patterns; step 8) performing a post-baking; and step 9) developing the negative electron-beam resist, so that the fabrication of the patterns is finished. According to the invention, it is possible to save 30-60% of the exposure time. Thus, the exposure efficiency is significantly improved, and the cost is greatly reduced. Further, the method is totally compatible with the CMOS processes, without the need of any special equipments.

Abstract: The present invention provides a method for removing polymer after etching a gate stack structure of high-K gate dielectric/metal gate. The method mainly comprises the following steps: 1): forming a gate stack structure of interface SiO2/high-K gate dielectric/metal gate/poly-silicon/hard mask in sequence on a silicon substrate with device isolations formed thereon; 2): forming a resist pattern by the lithography; 3): etching the gate stack structure; and 4): immersing the resultant structure of the step 3) in an etching solution to remove the polymer, wherein the etching solution consists of HF, HCl and water, the ratio of HF by volume is 0.2˜1% and the ratio of HCl by volume is 5˜15%. According to the present invention, the wet chemical etching using a mixed solution of HF and HCl is adopted and thus it is possible to completely remove the polymer remained on both sides of the gate stack and on the surface of the silicon substrate under the room temperature.