Patents by Inventor Quaizar Vohra

Quaizar Vohra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100061241
    Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric physically distributed among a set of chassis. The multi-stage switch fabric has a set of input buffers and a set of output ports. The switch core can be configured to be coupled to a set of edge devices. The apparatus can also include a controller implemented in hardware without software during operation and with software during configuration and monitoring. The controller can be coupled to the set of input buffers and the set of output ports. The controller can be configured to send a flow control signal to an input buffer from the set of input buffers when congestion at an output port from the set of output ports is predicted and before congestion in the switch core occurs.
    Type: Application
    Filed: June 30, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061391
    Abstract: In one embodiment, an apparatus can include a first edge device that can have a packet processing module. The first edge device can be configured to receive a packet. The packet processing module of the first edge device can be configured to produce cells based on the packet. A second edge device can have a packet processing module configured to reassemble the packet based on the cells. A multi-stage switch fabric can be coupled to the first edge device and the second edge device. The multi-stage switch fabric can define a single logical entity. The multi-stage switch fabric can have switch modules. Each switch module from the switch modules can have a shared memory device. The multi-stage switch fabric can be configured to switch the cells so that the cells are sent to the second edge device.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061367
    Abstract: In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric that has a set of stages physically distributed across a set of chassis. The set of stages collectively has a set of ingress ports and a set of egress ports. The switch core can be configured to be coupled to a set of peripheral processing devices via the set of ingress ports and the set of egress ports. The switch core can be configured to admit a set of cells associated with a packet into an ingress port from the set of ingress ports when delivery of the set of cells can be substantially guaranteed without loss through the multi-stage switch fabric.
    Type: Application
    Filed: June 30, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061394
    Abstract: In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric physically distributed across a plurality of chassis. The multi-stage switch fabric has a plurality of ingress ports and a plurality of egress ports. The switch core is configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports. The switch core is also configured to provide non-blocking connectivity at line rate between a first peripheral processing device disposed with a first chassis and a second peripheral processing device disposed within a second chassis.
    Type: Application
    Filed: June 30, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061242
    Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061240
    Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. The multi-stage switch fabric has a set of ingress ports and a set of egress ports. The switch core can be configured to be coupled to a set of edge devices via the set of ingress ports and the set of egress ports. The switch core can be configured to receive a packet from an ingress port from the set of ingress ports. The switch core can be configured to send a set of cells associated with the packet from the ingress port to an egress port from the set of egress ports without a store-and-forward delay associated with a zero-load latency for the switch core.
    Type: Application
    Filed: June 30, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
  • Publication number: 20100061389
    Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.
    Type: Application
    Filed: June 30, 2009
    Publication date: March 11, 2010
    Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra