Abstract: A circuit includes a driver circuit having a high side switch device and a low side switch device coupled to a load voltage node and a motor winding output. A controller operates the high side switch device and the low side switch device. The controller operates in a normal mode to supply current to the motor winding output for driving a motor winding when an external power supply is available to supply the load voltage node. In response to detecting a loss of the external power supply, the controller operates the high side switch device and the low side switch device in a boost mode to utilize a back electromotive force (BEMF) voltage from the motor winding to supply current to the load voltage node.

Abstract: A circuit includes a driver circuit having a high side switch device and a low side switch device coupled to a load voltage node and a motor winding output. A controller operates the high side switch device and the low side switch device. The controller operates in a normal mode to supply current to the motor winding output for driving a motor winding when an external power supply is available to supply the load voltage node. In response to detecting a loss of the external power supply, the controller operates the high side switch device and the low side switch device in a boost mode to utilize a back electromotive force (BEMF) voltage from the motor winding to supply current to the load voltage node.

Abstract: Command reordering in the hub interface unit (HIU) of Enhanced Direct Memory Access (EDMA) functions is described. Without command reordering in the EDMA, commands are issued by the HIU to the peripheral in order of issue. If the higher priority transfers are issued later by the EDMA, the previously issued lower priority transfers would block the higher priority transfers. Command reordering in the HIU causes transfers to be reordered and issued to the peripheral based on their priority. Reordering allows the EDMA and HIU to give due service to high priority transfer requests with decreased weight placed on the order in which the requests were issued.

Abstract: An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into a write buffer and acknowledges to the source port that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer and the EDMA then can acknowledge the port read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically.

Abstract: The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.

Abstract: The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.

Abstract: Command reordering in the hub-interface unit (HIU) of Enhanced Direct Memory Access (EDMA) functions is described. Without command reordering in the EDMA, commands are issued by the HIU to the peripheral in order of issue. If the higher priority transfers are issued later by the EDMA, the previously issued lower priority transfers would block the higher priority transfers. Command reordering in the HIU causes transfers to be reordered and issued to the peripheral based on their priority. Reordering allows the EDMA and HIU is to give due service to high priority transfer requests with decreased weight placed on the order in which the requests were issued.

Abstract: An extended direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into a write buffer and acknowledges to the source port that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer and the EDMA then can acknowledge the port read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically.

Abstract: A spatial light modulator (10) with a programmable format pixel array (14). The pixel array (14) has a programmable row address circuit (30), and a partitionable programmable column data loading circuit (32) which permits the array (14) to be operated in multiple formats compatible with NTSC, PAL, SECAM and other broadcasting standards. The pixel array (14) is of the DMD type. The array can be configured as 864.times.576 pixel array, a 768.times.576 pixel array, an 864.times.480 pixel array, or a 640.times.480 pixel array. This format is controlled by hardware (30,32) designed into the DMD chip. A partitionable shift register (32) has a MUXED input to provide testability, permitting some or all of the data input lines (D0-D53) to be utilized, and also allowing pixel data to be loaded back into the shift register (32) for functional verification. A programmable row address circuit (30) automatically addresses a subset of pixel rows as a function of a single input.

Abstract: A microprocessor (5) including a plurality of arithmetic logic units (42) is disclosed. At least one of the arithmetic logic units (42) includes a shifter circuit (50) for executing logical and arithmetic shift, rotate, and rotate-through-carry instructions in both the left and right directions, on data words of various lengths. The shifter (50) includes a series of input multiplexers (72, 74, 76, 78) for presenting the data word, carry bits, and extended sign bits to a first funnel shifter stage (80). Each of the multiplexers (72, 74, 76, 78) and first funnel shifter stage (80) are preferably realized by AND-OR-INVERT logic, to allow for 0 logic states and don't cares to be presented by the nonassertion of a control signal thereto. The shifter (50) is implemented as a right funnel shifter, with left shifts and rotates performed by presentation of the data word to the most significant bits of the first funnel shifter stage (80), followed by a right shift of the logical complement of the shift count.

Abstract: A spatial light modulator (SLM) device (30) having a pixel array (31) and an associated memory cell array (36). Each memory cell (10a) receives pixel data from a single bit-line that carries pixel data down columns of the memory cell array (36). Each memory cell (10a) has two latches (21, 25). A first latch (21) receives data from the bit-line. A second latch (25) receives data transferred from the first latch (21) in response to a transfer signal, and is in electrical communication with at least one address electrode (14) of each pixel (10) of the pixel array (31).

Abstract: A look-ahead flag generator generates a flag signal corresponding to the occurrence of a predetermined value stored in a counter (10). The output of the counter outputs any of a plurality of values, the values including the predetermined value and at least one boundary value that is one unit of increment or decrement displaced from the predetermined value. A clock signal source (13) is coupled to a first input of the counter (10) to indicate a decrement or an increment to the value stored in the counter (10). An up/down signal source (11) is coupled to a second input of the counter to indicate whether an increment or a decrement of the stored value should be performed. Predetermined states of the up/down signal and the clock signal are operable to cause a boundary value stored in the counter (10) to be changed to the predetermined value. A predecoder (12) is coupled to an output of counter (10) for decoding the boundary value. A latch (132) stores the decoded boundary value.