Patents by Inventor Rafael Rios
Rafael Rios has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923848Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.Type: GrantFiled: April 20, 2022Date of Patent: March 5, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11909391Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: February 20, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11901891Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: February 13, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11888479Abstract: A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.Type: GrantFiled: October 1, 2021Date of Patent: January 30, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11869939Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.Type: GrantFiled: March 24, 2022Date of Patent: January 9, 2024Assignee: Sony Group CorporationInventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Mark Armstrong, Rafael Rios, Abhijit Jayant Pethe, Willy Rachmady
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Patent number: 11863184Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: January 2, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11855627Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 13, 2022Date of Patent: December 26, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11855626Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: December 26, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11817859Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1 V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: November 14, 2023Assignee: KEPLER COMPUTING INC.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11811402Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.Type: GrantFiled: January 14, 2022Date of Patent: November 7, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11777504Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.Type: GrantFiled: November 29, 2022Date of Patent: October 3, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
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Publication number: 20230301113Abstract: A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Applicant: Kepler Computing Inc.Inventors: Noriyuki Sato, Tanay Gosavi, Rafael Rios, Amrita Mathuriya, Niloy Mukherjee, Mauricio Manfrini, Rajeev Kumar Dokania, Somilkumar J. Rathi, Sasikanth Manipatruni
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Patent number: 11764790Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.Type: GrantFiled: May 21, 2021Date of Patent: September 19, 2023Assignee: KEPLER COMPUTING INC.Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh, Sasikanth Manipatruni
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Patent number: 11757452Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.Type: GrantFiled: April 20, 2022Date of Patent: September 12, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11750197Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.Type: GrantFiled: April 20, 2022Date of Patent: September 5, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11742860Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.Type: GrantFiled: June 22, 2022Date of Patent: August 29, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
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Publication number: 20230251828Abstract: Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit.Type: ApplicationFiled: February 7, 2022Publication date: August 10, 2023Applicant: Kepler Computing Inc.Inventors: Amrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11721690Abstract: An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 15, 2021Date of Patent: August 8, 2023Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11716086Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11716085Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignee: Kepler Computing, Inc.Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya