Patents by Inventor Raghunath Reddy Kommidi

Raghunath Reddy Kommidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8400915
    Abstract: A packet switch includes a pipeline scheduler for scheduling packets according to a credit-based flow control protocol. A credit update pipeline stage initializes available credits for egress ports of the packet switch. A request pipeline stage generates packet requests for packets based on the available credits. A grant pipeline stage selects packets based on the ports requests and the available credits, and generates port grants for the selected packets. Additionally, the credit update stage updates the available credits based on the port grants. The packet switch routes the selected packets from ingress ports of the packet switch to the egress ports based on the port grants. In some embodiments, ingress ports generate enqueue requests based on the packets, an enqueue pipeline stage generates enqueue states based on the enqueue requests, and the request pipeline stage selects packets for routing based on the enqueue states and the available credits.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: March 19, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: David Alan Brown, Raghunath Reddy Kommidi, Sanjay T. Karambale
  • Patent number: 8391302
    Abstract: A packet switch includes ingress ports, each of which contains a random access memory having a storage capacity for storing data. An ingress controller of the packet switch allocates the storage capacity of each random access memory among transaction types of packets by allocating credits to each of the transactions types for the random access memory. Each ingress port accepts packets based on the transaction types of the packets and the credits of the random access memory in the ingress port. Moreover, the ingress port stores accepted packets in the random access memory of the ingress port. In further embodiments, the ingress controller dynamically reallocates the credits of the random access memory in the ingress port during operation of the packet switch.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: March 5, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Raghunath Reddy Kommidi, David Alan Brown
  • Patent number: 8284790
    Abstract: A packet switch receives packets at an ingress port, generates enqueue records for the packets, and stores the enqueue records in an enqueue structure. The enqueue record of a packet includes a pass flag for indicating whether a permissive passing rule is applicable to the packet. The packet switch determines a routing order for the packets stored in the ingress port based on the enqueue records and a set of ordering rules including the permissive passing rule. If a packet is blocked in the packet switch, the packet switch identifies an oldest unblocked routable packet stored in the ingress port based on the enqueue records and the set of ordering rules. Further, the packet switch routes the oldest unblocked routable packet through the packet switch. In this way, the packet switch allows the oldest unblocked routable packet to pass the blocked packet in the packet switch.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: October 9, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Raghunath Reddy Kommidi, David Alan Brown
  • Patent number: 8174969
    Abstract: A packet switch includes a flow control circuit for preventing a downstream ingress port of the packet switch from providing a non-posted packet to an upstream egress port of the packet switch when a downstream egress port of the packet switch is congested. As a result, congestion is reduced in the downstream egress port. Additionally, congestion is reduced in an upstream ingress port of the packet switch that receives completion packets in response to non-posted packets output from the upstream egress port and provides the completion packets to the downstream egress port. Because congestion is reduced in the upstream ingress port, latency is reduced for a completion packet received at the upstream ingress port and provided to another downstream egress port of the packet switch in response to a non-posted packet provided from another downstream ingress port to the upstream egress port and output from the packet switch.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: May 8, 2012
    Assignee: Integrated Device Technology, inc
    Inventors: Raghunath Reddy Kommidi, David Alan Brown