Patents by Inventor Rahoul Puri
Rahoul Puri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10860520Abstract: A system that allows access to a virtualized device is disclosed. The system may include a device, a processor, and a communication unit coupled to the device via a communication link. The device may include hardware resources configured to be shared by multiple threads executing on the processor. The communication unit may be configured to detect a request to access the device by the processor. In response to the detection of the request, the communication unit may send one or more instructions to the device via the communication link using a communication protocol.Type: GrantFiled: November 18, 2015Date of Patent: December 8, 2020Assignee: Oracle International CorporationInventors: Rahoul Puri, Rick C. Hetherington, Harry Stuimer, Hongping Li, John R. Feehrer
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Patent number: 10853303Abstract: An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.Type: GrantFiled: November 18, 2015Date of Patent: December 1, 2020Assignee: Oracle International CorporationInventors: John R. Feehrer, Matthew Cohen, Rahoul Puri, John Johnson, Alan Adamson, Julia Harper
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Patent number: 10817456Abstract: An apparatus and method for controlling a device with shared hardware resources to provide separate execution environments for control and data functions are disclosed. A processor may be configured to generate a first request to access control functions of the device in response to execution of a first thread, and generate a second request to access data functions of the device in response to execution of a second thread. A communication unit may send first indicative of the first request and second data indicative of the second request to the device via first and second ports, respectively.Type: GrantFiled: June 21, 2017Date of Patent: October 27, 2020Assignee: Oracle International CorporationInventors: John R. Feehrer, Matthew Cohen, Rahoul Puri, Tayfun Kocaoglu, John Johnson, David Kahn, Alan Adamson, Sriram Jayakumar, Julia Harper, Robert G. Sheldon, Mark Kanda, Aruna Jayakumar
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Patent number: 10296356Abstract: An apparatus and method for resetting a virtualized device are disclosed. The virtualized device may be coupled to a first port on a communication unit via a first link. The first port may send one or more instructions to the virtualized device via the first link using a first communication protocol. A processor may be configured to detect a reset condition for the virtualized device. In response to the detection of the reset condition for the virtualized device, the first port may disregard one or more transaction requests made by the virtualized device. The first port may further send an error message to the processor in response to receiving a Programmed Input/Output (PIO) request from the processor after the detection of the reset condition.Type: GrantFiled: November 18, 2015Date of Patent: May 21, 2019Assignee: Oracle International CorporationsInventors: John R. Feehrer, Sriram Jayakumar, Rahoul Puri, Matthew Cohen, Julia Harper, Alan Adamson, John Johnson
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Publication number: 20170286354Abstract: An apparatus and method for controlling a device with shared hardware resources to provide separate execution environments for control and data functions are disclosed. A processor may be configured to generate a first request to access control functions of the device in response to execution of a first thread, and generate a second request to access data functions of the device in response to execution of a second thread. A communication unit may send first indicative of the first request and second data indicative of the second request to the device via first and second ports, respectively.Type: ApplicationFiled: June 21, 2017Publication date: October 5, 2017Inventors: John R. Feehrer, Matthew Cohen, Rahoul Puri, Tayfun Kocaoglu, John Johnson, David Kahn, Alan Adamson, Sriram Jayakumar, Julia Harper, Robert G. Sheldon, Mark Kanda
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Publication number: 20170139721Abstract: An apparatus and method for resetting a virtualized device are disclosed. The virtualized device may be coupled to a first port on a communication unit via a first link. The first port may send one or more instructions to the virtualized device via the first link using a first communication protocol. A processor may be configured to detect a reset condition for the virtualized device. In response to the detection of the reset condition for the virtualized device, the first port may disregard one or more transaction requests made by the virtualized device. The first port may further send an error message to the processor in response to receiving a Programmed Input/Output (PIO) request from the processor after the detection of the reset condition.Type: ApplicationFiled: November 18, 2015Publication date: May 18, 2017Inventors: John R. Feehrer, Sriram Jayakumar, Rahoul Puri, Matthew Cohen, Julia Harper, Alan Adamson, John Johnson
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Publication number: 20170139799Abstract: A system that allows access to a virtualized device is disclosed. The system may include a device, a processor, and a communication unit coupled to the device via a communication link. The device may include hardware resources configured to be shared by multiple threads executing on the processor. The communication unit may be configured to detect a request to access the device by the processor. In response to the detection of the request, the communication unit may send one or more instructions to the device via the communication link using a communication protocol.Type: ApplicationFiled: November 18, 2015Publication date: May 18, 2017Inventors: Rahoul Puri, Rick C. Hetherington, Harry Stuimer, Hongping Li, John R. Feehrer
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Publication number: 20170139873Abstract: An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.Type: ApplicationFiled: November 18, 2015Publication date: May 18, 2017Inventors: John R. Feehrer, Matthew Cohen, Rahoul Puri, John Johnson, Alan Adamson, Julia Harper
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Patent number: 8176304Abstract: An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.Type: GrantFiled: October 22, 2008Date of Patent: May 8, 2012Assignee: Oracle America, Inc.Inventors: Rahoul Puri, Arvind Srinivasan, Louise Y. Yeung, Marcelino M. Dignum, John E. Watkins
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Patent number: 8145967Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.Type: GrantFiled: October 12, 2007Date of Patent: March 27, 2012Assignee: Oracle America, Inc.Inventors: Arvind Srinivasan, Rahoul Puri
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Patent number: 8078928Abstract: A system and method for verifying the transmit path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., hosts, input buses) and output sources (e.g., output buses, networks) is modeled in a verification layer that employs multiple queues to simulate receipt of input data, submission to an output port and transmission from the device. Call backs are employed to signal completion of events related to receipt of data at the device and modeling of data processing within the verification layer. As call backs are resolved, corresponding tasks are executed to advance the processing of the data through the verification layer. A device-specific algorithm is executed in the verification layer to predict the ordering of output from the device, and that output is compared to the predicted output by a transmission checker.Type: GrantFiled: October 12, 2007Date of Patent: December 13, 2011Assignee: Oracle America, Inc.Inventors: Arvind Srinivasan, Rahoul Puri
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Patent number: 8032669Abstract: A universal DMA (Direct Memory Access) engine can be dynamically configured to function in either a receive or transmit mode. DMAs are logically assembled and bound as needed, without limitation to a fixed, pre-determined number of receive engines and transmit engines. Because a DMA engine may be dynamically assembled to support the flow of data in either direction, varied usage models are enabled, and components used to assemble a receive DMA engine for one application may be subsequently used to assemble a transmit engine for a different application. An application may request a specific number of each type of engine, depending on the nature of its input/output traffic. The number of receive or transmit engines can be dynamically increased or decreased without suspending or rebooting the host. A universal DMA architecture provides a unified software framework, thereby decreasing the complexity of the software and the hardware gate count cost.Type: GrantFiled: January 20, 2008Date of Patent: October 4, 2011Assignee: Oracle America, Inc.Inventors: Rahoul Puri, Arvind Srinivasan, Elisa Rodrigues
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Patent number: 8006016Abstract: A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.Type: GrantFiled: January 18, 2011Date of Patent: August 23, 2011Assignee: Oracle America, Inc.Inventors: Shimon Muller, Rahoul Puri, Michael Wong
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Patent number: 7992144Abstract: A network system that provides for separating and isolating control of processing entities in a network interface. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. One of the processing entities operates as a hypervisor to configure control resources to isolate operation of the plurality of data processing partitions to process data transported by the network system. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing.Type: GrantFiled: April 4, 2005Date of Patent: August 2, 2011Assignee: Oracle America, Inc.Inventors: Ariel Hendel, Yatin Gajjar, May Lin, Rahoul Puri, Michael Wong
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Patent number: 7987306Abstract: A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.Type: GrantFiled: April 4, 2005Date of Patent: July 26, 2011Assignee: Oracle America, Inc.Inventors: Shimon Muller, Rahoul Puri, Michael Wong
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Publication number: 20110110380Abstract: A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and in parallel to and from a memory system so that one or more of the plurality of memory access channels operate efficiently in the presence of arbitrary memory latencies across multiple requests is disclosed. The network interface includes a plurality of memory access channels.Type: ApplicationFiled: January 18, 2011Publication date: May 12, 2011Inventors: Shimon Muller, Rahoul Puri, Michael Wong
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Patent number: 7889734Abstract: A method and apparatus for mapping sessions to preassigned processing entities in a network system. A network interface unit is operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions based upon an association with a predetermined session.Type: GrantFiled: April 5, 2005Date of Patent: February 15, 2011Assignee: Oracle America, Inc.Inventors: Ariel Hendel, Yatin Gajjar, May Lin, Rahoul Puri, Michael Wong
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Patent number: 7836328Abstract: A method and apparatus for recovering from errors occurring during system bus transactions. An input/output device such as a network interface unit (NIU) issues read and write operations across a meta interface coupling the device to host bus (glue) logic. The host bus logic translates the operations into system bus transactions. The device maintains a set of reusable identifiers for identifying the operations, and a table maintained by the device or the host bus logic maps the operation identifiers to transaction identifiers identifying the system bus transactions spawned to perform the operations. If a bus transaction encounters an unrecoverable error, the host bus logic reports the error to the device and drops any further data received from other bus transactions performed for the same operation. The device marks the operation's identifier as dirty, to prevent its reuse. The operation identifier may be reused after software clears the error condition.Type: GrantFiled: May 4, 2006Date of Patent: November 16, 2010Assignee: Oracle America, Inc.Inventors: Rahoul Puri, John E. Watkins, Arvind Srinivsan, Babu R. Kandimalla, Nimita Taneja
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Patent number: 7779164Abstract: A network system includes a network interface unit operably connected to a plurality of processing entities and a plurality of memory units that define a shared memory space. The network interface unit further comprises a memory access module that includes a plurality of memory access channels, a packet classifier, and a plurality of scheduling control modules that are operable to control processing of data transported by the network. In various embodiments of the invention, predetermined subsets of the plurality of processing entities are operably associated with predetermined subsets of the plurality of memory units thereby defining a plurality of asymmetrical data processing partitions. The packet classifier is operable to provide an association between packets and the plurality of asymmetrical data processing partitions. The asymmetrical data processing partitions are scalable by adding additional processing entities.Type: GrantFiled: April 4, 2005Date of Patent: August 17, 2010Assignee: Oracle America, Inc.Inventors: Ariel Hendel, Yatin Gajjar, May Lin, Rahoul Puri, Michael Wong
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Patent number: 7706289Abstract: A system and method for validating packet classification within an input/output device or component. Based on a target DMA engine within the device, and a protocol path for testing the DMA engine, sets of packet attributes are generated and used to format packets for input to the device. The output of the device is examined to determine if the correct DMA engine was used within the device. The DMA policy specifying which DMA engine to use for a particular packet configuration or set of protocol attributes can be dynamically replaced or modified without halting the validation process.Type: GrantFiled: December 30, 2007Date of Patent: April 27, 2010Assignee: Oracle America, Inc.Inventors: Rahoul Puri, Arvind Srinivasan, Saranga P. Pogula