Patents by Inventor Rainer Bruchhaus
Rainer Bruchhaus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9001558Abstract: A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit is measured and an electrical variable is selected for this measurement, to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A instate A1 makes a different contribution than the memory cell B in state B1. The two state combinations A1 and B0 or A0 and B1 then result in differing values for the electrical variable that is measured by way of the series circuit. These state combinations can thus be distinguished from each other without having to change the logic state of the memory element during reading.Type: GrantFiled: February 3, 2012Date of Patent: April 7, 2015Assignees: Forschungszentrum Juelich GmbH, Rheinisch-Westfaelische Technische Hochschule Aachen (RWTH)Inventors: Roland Daniel Rosezin, Florian Lentz, Rainer Bruchhaus, Eike Linn, Ilia Valov, Rainer Waser, Stefan Tappertzhofen, Lutz Nielen
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Publication number: 20140036574Abstract: A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit is measured and an electrical variable is selected for this measurement, to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A instate A1 makes a different contribution than the memory cell B in state B1. The two state combinations A1 and B0 or A0 and B1 then result in differing values for the electrical variable that is measured by way of the series circuit. These state combinations can thus be distinguished from each other without having to change the logic state of the memory element during reading.Type: ApplicationFiled: February 3, 2012Publication date: February 6, 2014Applicant: Forschungszentrum Juelich GmbHInventors: Roland Daniel Rosezin, Florian Lentz, Rainer Bruchhaus, Eike Linn, Ilia Valov, Rainer Waser, Stefan Tappertzhofen, Lutz Nielen
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Patent number: 8063394Abstract: According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.Type: GrantFiled: October 8, 2008Date of Patent: November 22, 2011Assignee: Qimonda AGInventors: Dieter Andres, Rainer Bruchhaus, Ulrike Gruening-Von Schwerin, Ulrich Klostermann, Franz Kreupl, Michael Kund, Petra Majewski, Christian Ruester, Bernhard Ruf, Ralf Symanczyk, Klaus-Dieter Ufert
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Publication number: 20100084741Abstract: According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.Type: ApplicationFiled: October 8, 2008Publication date: April 8, 2010Inventors: Dieter Andres, Rainer Bruchhaus, Ulrike Gruening-Von Schwerin, Ulrich Klostermann, Franz Kreupl, Michael Kund, Petra Majewski, Christian Ruester, Bernhard Ruf, Ralf Symanczyk, Klaus-Dieter Ufert
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Publication number: 20100001252Abstract: An integrated circuit includes a plurality of programmable metallization memory cells. Each memory cell includes a memory element having a first electrode layer, a second electrode layer, and a resistance changing material layer arranged between the first electrode layer and the second electrode layer. The resistance changing material layer includes an active matrix material layer made of a chalcogenide material including at least one chalcogen and at least one electropositive element, wherein the chalcogenide material is not GeS, GeSe, AgSe or CuS.Type: ApplicationFiled: July 1, 2008Publication date: January 7, 2010Inventors: Ralf Symanczyk, Rainer Bruchhaus
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Publication number: 20090190388Abstract: A method of fabricating a resistive storage device is provided. The method generally comprises providing an electrode structure stack comprising a first electrode and an electrode structure mask arranged at the first electrode, forming a support structure at least partly at the electrode structure mask, removing the electrode structure mask to leave a storage region window in the support structure, and forming a resistive storage region in the storage region window at the first electrode.Type: ApplicationFiled: January 24, 2008Publication date: July 30, 2009Inventors: Rainer Bruchhaus, Ulrike Gruening Von Schwerin
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Patent number: 7522444Abstract: The present invention is related to a memory circuit comprising: a resistive memory element comprising a programmable metallization cell, a bit line, a selection transistor operable to address the resistive memory element for coupling the resistive memory element to the bit line, and a further transistor coupled with the resistive memory element for applying a predefined potential at a node between the selection transistor and the resistive memory element.Type: GrantFiled: March 13, 2006Date of Patent: April 21, 2009Assignee: Infineon Technologies AGInventors: Corvin Liaw, Heinz Hoenigschmid, Rainer Bruchhaus
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Patent number: 7456456Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a capacitor including a lower electrode disposed above the semiconductor substrate, a dielectric film disposed above the lower electrode, and an upper electrode disposed above the dielectric film, the upper electrode including metal oxide formed of ABO3 perovskite oxide and containing at least an Ru element as a B site element, and a metal film containing a Ti element being disposed between the dielectric film and the upper electrode.Type: GrantFiled: December 27, 2006Date of Patent: November 25, 2008Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies AGInventors: Hiroshi Itokawa, Koji Yamakawa, Rainer Bruchhaus
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Patent number: 7378700Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.Type: GrantFiled: March 9, 2006Date of Patent: May 27, 2008Assignee: Infineon Technologies AGInventors: Jingyu Lian, Nicolas Nagel, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, Uwe Wellhausen
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Patent number: 7361549Abstract: The invention provides a method for fabricating a memory device having memory cells which are formed on a microstructured driving unit (100), in which method a shaping layer (104) is provided and is patterned in such a manner that vertical trench structures (105) are formed perpendicular to the surface of the driving unit (100). Deposition of a seed layer (106) on side walls (105a) of the trench structures (105) allows a crystallization agent (107) which has filled the trench structures (105), during crystallization, to have grain boundaries perpendicular to electrode surfaces that are to be formed. This provides memory cells based on vertical ferroelectric capacitors in a chain FeRAM structure.Type: GrantFiled: July 20, 2005Date of Patent: April 22, 2008Assignee: Infineon Technologies AGInventors: Rainer Bruchhaus, Martin Gutsche
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Publication number: 20080073751Abstract: A memory cell includes a substrate, a first electrode disposed over the substrate a resistance element disposed over the first electrode, a second electrode disposed over the resistance element, the second electrode comprising an alloy, the alloy being formed from a first metal layer deposited on the resistance element, a second metal layer deposited on the first metal layer and heating the first and second metal layers.Type: ApplicationFiled: September 21, 2006Publication date: March 27, 2008Inventor: Rainer Bruchhaus
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Patent number: 7348619Abstract: A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.Type: GrantFiled: August 31, 2005Date of Patent: March 25, 2008Assignee: Infineon Technologies AGInventors: Rainer Bruchhaus, Martin Gutsche, Cay-Uwe Pinnow
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Patent number: 7316980Abstract: Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.Type: GrantFiled: October 2, 2003Date of Patent: January 8, 2008Assignee: Infineon Technologies AGInventors: Haoren Zhuang, Ulrich Egger, Rainer Bruchhaus, Karl Hornik, Jenny Lian, Stefan Gernhardt
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Publication number: 20070211514Abstract: The present invention is related to a memory circuit comprising: a resistive memory element comprising a programmable metallization cell, a bit line, a selection transistor operable to address the resistive memory element for coupling the resistive memory element to the bit line, and a further transistor coupled with the resistive memory element for applying a predefined potential at a node between the selection transistor and the resistive memory element.Type: ApplicationFiled: March 13, 2006Publication date: September 13, 2007Inventors: Corvin Liaw, Heinz Hoenigschmid, Rainer Bruchhaus
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Publication number: 20070111334Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a capacitor including a lower electrode disposed above the semiconductor substrate, a dielectric film disposed above the lower electrode, and an upper electrode disposed above the dielectric film, the upper electrode including metal oxide formed of ABO.sub.3 perovskite oxide and containing at least an Ru element as a B site element, and a metal film containing a Ti element being disposed between the dielectric film and the upper electrode.Type: ApplicationFiled: December 27, 2006Publication date: May 17, 2007Applicants: KABUSHHIKI KAISHA TOSHIBA, INFINEON TECNOLOGIES AGInventors: Hiroshi ITOKAWA, Koji Yamakawa, Rainer Bruchhaus
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Patent number: 7198959Abstract: In a process for fabricating a ferrocapacitor comprising providing ferroelectric PZT elements over an Al2O3 layer, the Al2O3 layer is covered with a seed layer comprising layers of PZT and TiO2. Then a thicker layer of PZT is formed over the seed layer and crystallized. By this process, the crystallinity of the thick PZT layer is much improved, and its orientation is improved to be in the (111) direction. Furthermore, the seed layer reduces downward diffraction of Pb from the thick PZT layer, such as through the Al2O3 into a TEOS structure beneath.Type: GrantFiled: June 30, 2004Date of Patent: April 3, 2007Assignee: Infineon Technologies AGInventors: Karl Hornik, Rainer Bruchhaus, Bum-Ki Moon
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Patent number: 7199002Abstract: A process for the fabrication of a ferroelectric capacitor comprising depositing a layer of Ti 5 over an insulating layer 3 of Al2O3, and oxidising the Ti layer to form a TiO2 layer 7. Subsequently, a layer of PZT 9 is formed over the TiO2 layer 7. The PZT layer 9 is subjected to an annealing step in which, due to the presence of the TiO2 layer 7 it crystallises to form a layer 11 with a high degree of (111)-texture.Type: GrantFiled: August 29, 2003Date of Patent: April 3, 2007Assignee: Infineon Technologies AGInventors: Karl Hornik, Rainer Bruchhaus, Nicolas Nagel
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Patent number: 7183121Abstract: A process for fabricating a ferrocapacitor comprises etching a layer of amorphous PZT formed over a layer having a low concentration of nucleation centres for PZT crystallisatlon. The etching step forms individual PZT elements. The side surfaces of the PZT elements are then coated with a layer of a material which promotes crystallisation of the PZT, such as one having a high concentration of PZT crystallisation centres (e.g. TiO2), and a PZT annealing step is carried out. The result is that the PZT has a high degree of crystallisation, with grain boundaries extending substantially horizontally through the PZT elements.Type: GrantFiled: September 26, 2003Date of Patent: February 27, 2007Assignee: Infineon Technologies AGInventors: Rainer Bruchhaus, Karl Hornik
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Patent number: 7098142Abstract: A method of etching a ferroelectric device 100 having a ferroelectric layer 112 between a top and a bottom electrode 114, 108 is disclosed herein. Hardmasks 116, 118 are deposited on the top electrode 114, two or more hardmasks being spaced apart by narrow first regions 115 and spaced apart from other hardmasks by wider second regions 117. The top electrode 114 and ferroelectric layer 112 are then etched to pattern the top electrode 114 thus forming capacitors 102, 104, and the bottom electrode 108 is etched by a process in which the second regions are etched more slowly than the second regions. Those capacitors having a first region between them have a common bottom electrode 108, but in the second regions the bottom electrode is severed. To pattern the bottom electrode 108, a fluorine-based chemistry followed thereafter by a CO-based chemistry are used in a two step etching process.Type: GrantFiled: February 26, 2003Date of Patent: August 29, 2006Assignee: Infineon Technologies AGInventors: Ulrich Egger, Haoren Zhuang, Rainer Bruchhaus
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Publication number: 20060151819Abstract: An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.Type: ApplicationFiled: March 9, 2006Publication date: July 13, 2006Inventors: Jingyu Lian, Nicolas Nagel, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, Uwe Wellhausen