Abstract: Error correction is proposed in which a syndrome calculation is carried out in a code domain of a second code and an efficient error correction algorithm is carried out in a code domain of a first code.

Abstract: Error correction is proposed, wherein, on the basis of a data word, a syndrome calculation is carried out with a matrix M on the basis of a matrix H of a code, and, if the result of the syndrome calculation reveals that the data word is erroneous, the result of the syndrome calculation is transformed by means of a linear mapping. Next, an error vector is determined on the basis of the result of the linear mapping by means of an efficient error correction algorithm and the erroneous data word is corrected on the basis of the error vector.

Abstract: According to one exemplary embodiment, an integrated circuit is described, comprising multiple noise sources, each noise source being configured to output a respective set of noise bits for a random vector, a combinational logic circuit configured to process a noise bit vector, corresponding to a concatenation of the bits of the sets of noise bits, in accordance with a multiplication by a matrix to produce a processed noise bit vector, with the result that the processed noise bit vector comprises more bits than each of the sets of noise bits and comprises fewer bits than the noise bit vector; and a post-processing logic circuit configured to generate the random vector from the processed noise bit vector.

Abstract: An integrated circuit includes a receiver configured to receive a message word and an integrated hardware decoding circuit. The decoding circuit includes a calculation unit to calculate a syndrome of the message word according to a predetermined BCH code, a logarithmization unit to establish a logarithm of each of one or more syndrome components, an arithmetic circuit to establish a logarithm of each of one or more zeros of the error locator polynomial of the BCH code on the basis of the logarithms of the syndrome components, and a bit inverter circuit to invert the one or more bits of the message word, the positions of which are specified by the logarithms of the zeros of the error locator polynomial. The integrated circuit further includes a data processing circuit to process further the message word processed by the bit inverter circuit.

Abstract: A device for generating a random number is suggested, the device comprising at least two shift registers, a transformation function that generates the random number based on at least one cell of each of the at least two shift registers.

Abstract: A data processing device includes a Physical Unclonable Function value source which is set up to provide a reference Physical Unclonable Function value and a plurality of subsequent Physical Unclonable Function values, the reference Physical Unclonable Function value and each subsequent Physical Unclonable Function value having a multiplicity of binary components, a determination device which is set up to determine a set of components, the value of which is identical in the plurality of subsequent Physical Unclonable Function values, and a Physical Unclonable Function reconstruction device which is set up to reconstruct the reference Physical Unclonable Function value from the subsequent Physical Unclonable Function values assuming that the values of the determined components in the subsequent Physical Unclonable Function value match the values of the determined components in the reference Physical Unclonable Function value.

Abstract: An integrated circuit includes a receiver configured to receive a message word and an integrated hardware decoding circuit. The decoding circuit includes a calculation unit to calculate a syndrome of the message word according to a predetermined BCH code, a logarithmization unit to establish a logarithm of each of one or more syndrome components, an arithmetic circuit to establish a logarithm of each of one or more zeros of the error locator polynomial of the BCH code on the basis of the logarithms of the syndrome components, and a bit inverter circuit to invert the one or more bits of the message word, the positions of which are specified by the logarithms of the zeros of the error locator polynomial. The integrated circuit further includes a data processing circuit to process further the message word processed by the bit inverter circuit.

Abstract: A method for determining an error vector for a data word according to a Reed-Muller Code includes determining the syndrome of the error vector according to the Reed-Muller Code, expanding the syndrome with zeroes to 1 bit length less than the length of the Reed-Muller Code, determining a code word of a Simplex Code of 1 bit length less than the length of the Reed-Muller Code whose difference to the expanded syndrome has a weight below a first threshold or equal to or above a second threshold, expanding the difference between the determined code word and the expanded syndrome by a zero, and outputting the expanded difference as error vector if its weight is below the first threshold or outputting the inverted expanded difference as error vector if the weight of the expanded difference is equal to or above the second threshold.

Abstract: In various embodiments, a method for determining an error vector in a data word is provided. The method includes determining the syndrome of the error vector, successively generating code words by cyclically interchanging one or more predefined code words, forming, for each code word generated, the sum of the syndrome supplemented with zeros to the data word length and the code word, and checking, for the code word, whether the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words, and determining the error vector as the sum of the syndrome and the code word for which the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words.

Abstract: A decoder includes a feedback shift register having a plurality of register elements that implement a simplex code and take a register vector for determining an appropriate syndrome fed into the feedback shift register and stored in the plurality of register elements. A combination device algebraically combines a subset of the register elements and provides a combination result vector. A majority decision-making unit ascertains a most frequently occurring value within the combination result vector and provides it as a decision result. An input selector connects an input of the feedback shift register to an input interface arrangement or to an output of the majority decision-making unit, and provides an input vector by the input interface arrangement and corresponds to the ascertained form of the physical unclonable properties as a register vector and, and provides a decision vector comprising the decision result and further decision results as a register vector.

Abstract: A data processing device includes a Physical Unclonable Function value source which is set up to provide a reference Physical Unclonable Function value and a plurality of subsequent Physical Unclonable Function values, the reference Physical Unclonable Function value and each subsequent Physical Unclonable Function value having a multiplicity of binary components, a determination device which is set up to determine a set of components, the value of which is identical in the plurality of subsequent Physical Unclonable Function values, and a Physical Unclonable Function reconstruction device which is set up to reconstruct the reference Physical Unclonable Function value from the subsequent Physical Unclonable Function values assuming that the values of the determined components in the subsequent Physical Unclonable Function value match the values of the determined components in the reference Physical Unclonable Function value.

Abstract: A method for reconstructing a first vector from a second vector includes: storing code for the row vectors according to a first code and a second code; correcting the row vectors of the second vector corresponding to the first vector so that the row vectors of the second vector have the same code as the row vectors of the first vector; calculating the code of the column vectors of the second vector according to the second code; comparing the code of the row vectors of the second vector with the code of the column vectors of the first vector; identifying the columns in which the first vector is unequal to the second vector; the rows in which the first vector is unequal to the second vector; and the components in which the first vector is not equal to the second vector, and correcting the components of the second vector.

Abstract: A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory.

Abstract: A method for determining an error vector for a data word according to a Reed-Muller Code includes determining the syndrome of the error vector according to the Reed-Muller Code, expanding the syndrome with zeroes to 1 bit length less than the length of the Reed-Muller Code, determining a code word of a Simplex Code of 1 bit length less than the length of the Reed-Muller Code whose difference to the expanded syndrome has a weight below a first threshold or equal to or above a second threshold, expanding the difference between the determined code word and the expanded syndrome by a zero, and outputting the expanded difference as error vector if its weight is below the first threshold or outputting the inverted expanded difference as error vector if the weight of the expanded difference is equal to or above the second threshold.

Abstract: A device for generating a random number is suggested, the device comprising at least two shift registers, a transformation function that generates the random number based on at least one cell of each of the at least two shift registers.

Abstract: In various embodiments, a method for determining an error vector in a data word is provided. The method includes determining the syndrome of the error vector, successively generating code words by cyclically interchanging one or more predefined code words, forming, for each code word generated, the sum of the syndrome supplemented with zeros to the data word length and the code word, and checking, for the code word, whether the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words, and determining the error vector as the sum of the syndrome and the code word for which the sum of the syndrome supplemented with zeros to the data word length and the code word has a minimum weight among all code words.

Abstract: A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF At and performing a preliminary correction of the potentially erroneous PUF At by means of a stored correction vector Deltat-1, to obtain a preliminarily corrected PUF Bt. The PUF A is reconstructed from the preliminarily corrected PUF Bt by means of an error correction algorithm. A corresponding apparatus is also provided.

Abstract: An embodiment relates to a method for data processing that includes reading data, the data comprising overhead information and payload information, and determining a state of each portion of the data, wherein the state is one of a first binary state, a second binary state, and an undefined state. The method also includes decoding at least one portion of data that has an undefined state based on its location and based on the overhead information.

Abstract: An embodiment relates to a method for data processing that includes reading data, the data comprising overhead information and payload information, and determining a state of each portion of the data, wherein the state is one of a first binary state, a second binary state, and an undefined state. The method also includes decoding at least one portion of data that has an undefined state based on its location and based on the overhead information.

Abstract: A method for reconstructing a first vector from a second vector includes: storing code for the row vectors according to a first code and a second code; correcting the row vectors of the second vector corresponding to the first vector so that the row vectors of the second vector have the same code as the row vectors of the first vector; calculating the code of the column vectors of the second vector according to the second code; comparing the code of the row vectors of the second vector with the code of the column vectors of the first vector; identifying the columns in which the first vector is unequal to the second vector; the rows in which the first vector is unequal to the second vector; and the components in which the first vector is not equal to the second vector, and correcting the components of the second vector.