Patents by Inventor Rajasekhar Reddy Allu

Rajasekhar Reddy Allu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240089425
    Abstract: Devices, systems, and methods detect an image frame freeze condition. An example device includes a core logic circuit configured to generate statistics for received image data associated with an image frame, perform a census transform on pixel values of the image data to generate census transformed data, arrange the census transformed data into a binary string having a binary value, and generate transformed image data by replacing a select pixel value of the pixel values of the image data with a decimal value corresponding to the binary value; a load/store engine (LSE) coupled to the core logic circuit, the LSE configured to determine a cyclic redundancy check (CRC) value based on at least one of the image data, the transformed image data, and at least one statistic of the statistics; and an interface configured to transmit the CRC value to a host device.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Niraj Nandan, Brian Chae, Mihir Mody, Rajasekhar Reddy Allu
  • Patent number: 11915442
    Abstract: An apparatus and method for geometrically correcting an arbitrary shaped input frame and generating an undistorted output frame. The method includes capturing arbitrary shaped input images with multiple optical devices and processing the images, identifying redundant blocks and valid blocks in each of the images, allocating an output frame with an output frame size and dividing the output frame into regions shaped as a rectangle, programming the apparatus and disabling processing for invalid blocks in each of the regions, fetching data corresponding to each of the valid blocks and storing in an internal memory, interpolating data for each of the regions with stitching and composing the valid blocks for the output frame and displaying the output frame on a display module.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody, Gang Hua, Brian Okchon Chae, Shashank Dabral, Hetul Sanghvi, Vikram VijayanBabu Appia, Sujith Shivalingappa
  • Patent number: 11875047
    Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: January 16, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Mihir Narendra Mody, Niraj Nandan, Rajasekhar Reddy Allu
  • Patent number: 11863713
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for image frame freeze detection. An example hardware accelerator includes a core logic circuit to generate second image data based on first image data associated with a first image frame, the second image data corresponding to at least one of processed image data, transformed image data, or one or more image data statistics, a load/store engine (LSE) coupled to the core logic circuit, the LSE to determine a first CRC value based on the second image data obtained from the core logic circuit, and a first interface coupled to a second interface, the second interface coupled to memory, the first interface to transmit the first CRC value obtained from the memory to a host device.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 2, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Niraj Nandan, Brian Chae, Mihir Mody, Rajasekhar Reddy Allu
  • Publication number: 20230419462
    Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.
    Type: Application
    Filed: September 12, 2023
    Publication date: December 28, 2023
    Inventors: Gang Hua, Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody
  • Publication number: 20230336887
    Abstract: In an advanced driver-assistance system (ADAS), RAW sensor image processing for a machine vision (MV) application is important. Due to different color, e.g., red/green/blue (RGB), color components, being focused by the lens at different locations in image plane, the lateral chromatic aberration phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) components.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 19, 2023
    Inventors: Gang HUA, Rajasekhar Reddy ALLU, Mihir Narendra MODY, Niraj NANDAN, Mayank MANGLA, Pandy KALIMUTHU
  • Publication number: 20230291864
    Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Inventors: Mihir Narendra MODY, Brijesh JADAV, Gang HUA, Niraj NANDAN, Rajasekhar Reddy ALLU, Ankur ANKUR, Mayank MANGLA
  • Patent number: 11756169
    Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: September 12, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Gang Hua, Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody
  • Patent number: 11743612
    Abstract: In the advanced driver-assistance systems (ADAS) field, RAW sensor image processing for machine vision (MV) applications can be of critical importance. Due to red/green/blue (RGB) image components being focused by the lens at different locations in image plane, the lateral chromatic aberration (LCA) phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) modules.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: August 29, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Gang Hua, Rajasekhar Reddy Allu, Mihir Narendra Mody, Niraj Nandan, Mayank Mangla, Pandy Kalimuthu
  • Publication number: 20230239585
    Abstract: Local automatic white balance (AWB) of wide dynamic range (WDR) images is provided. Methods and systems include collecting, by an image signal processor (ISP), statistics for local AWB from at least one wide dynamic range (WDR) image received by the ISP; generating, by a processor, based on the statistics, local gain lookup tables (LUTs), one for each color channel represented in the WDR image(s), each local gain LUT providing a correlation between gain and intensity; and storing the local gain LUTs. Further processing includes, for each of multiple pixels of a WDR image to be output calculating an intensity value, accessing the local gain LUT for the color channel corresponding to that pixel using the calculated intensity value to identify a corresponding local gain value, and applying the local gain value to that pixel.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Inventors: Gang Hua, Shashank Dabral, Mihir Narendra Mody, Rajasekhar Reddy Allu, Niraj Nandan
  • Publication number: 20230229610
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.
    Type: Application
    Filed: March 27, 2023
    Publication date: July 20, 2023
    Inventors: Niraj Nandan, Rajasekhar Reddy Allu, Brian Chae, Mihir Mody
  • Publication number: 20230199339
    Abstract: In the advanced driver-assistance systems (ADAS) field, RAW sensor image processing for machine vision (MV) applications can be of critical importance. Due to red/green/blue (RGB) image components being focused by the lens at different locations in image plane, the lateral chromatic aberration (LCA) phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) modules.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Inventors: Gang HUA, Rajasekhar Reddy ALLU, Mihir Narendra MODY, Niraj NANDAN, Mayank MANGLA, Pandy KALIMUTHU
  • Publication number: 20230169689
    Abstract: Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Gang HUA, Mihir Narendra MODY, Niraj NANDAN, Shashank DABRAL, Rajasekhar Reddy ALLU, Denis Roland BEAUDOIN
  • Publication number: 20230171512
    Abstract: A technique for image processing, comprising: receiving input image data, wherein the image data is companded into a first bit depth, wherein the image data includes incomplete color values for pixels of the image data, and wherein the image data is associated with a first color space, interpolating the image data to generate color values for the incomplete color values for pixels of the image data, expanding the image data from the first bit depth to a second bit depth, wherein the color values of the expanded image data have a linear dynamic range, and wherein the second bit depth is higher than the first bit depth, converting the color values for pixels of the expanded image data from the first color space to a second color space, and compressing the color values for pixels of the image data to a third bit depth, the third bit depth lower than the second bit depth, and wherein the compressed color values have a nonlinear dynamic range.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Gang HUA, Mihir Narendra MODY, Niraj NANDAN, Shashank DABRAL, Rajasekhar Reddy ALLU, Denis Roland BEAUDOIN
  • Patent number: 11653105
    Abstract: A method for local automatic white balance (AWB) of wide dynamic range (WDR) images is provided that includes collecting statistics for local AWB by an image signal processor (ISP) from a first WDR image generated by the ISP, receiving, by the ISP, a plurality of local gain lookup tables (LUTs), one for each color channel, wherein the plurality of local gain LUTs is generated using the statistics, and applying, by the ISP, a gain value to each pixel in a second WDR image generated by the ISP, wherein the gain value for the pixel is determined by the ISP using the local gain LUT for the color channel of the pixel.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: May 16, 2023
    Assignee: Texas Instmments Incorporated
    Inventors: Gang Hua, Shashank Dabral, Mihir Narendra Mody, Rajasekhar Reddy Allu, Niraj Nandan
  • Patent number: 11637961
    Abstract: Disclosed examples include integrated circuits, merge circuits and methods of processing multiple-exposure image data, in which a single pre-processing circuit is used for pre-processing first input exposure data associated with a first exposure of the image, and then for pre-processing second input exposure data associated with a second exposure of the image, and the first and second pre-processed exposure data are merged to generate merged image data for tone mapping and other post-processing. An example merge circuit includes a configurable gain circuit to apply a gain to the first and/or second exposure data, as well as a configurable weighting circuit with a weight calculation circuit and a motion adaptive filter circuit to compute a first and second weight values for merging the pre-processed first and second exposure data.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 25, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Shashank Dabral, Rajasekhar Reddy Allu
  • Publication number: 20230117485
    Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Inventors: Mihir Narendra MODY, Niraj NANDAN, Rajasekhar Reddy ALLU
  • Patent number: 11615043
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed herein to enable data aggregation and pattern adaptation in hardware acceleration subsystems. In some examples, a hardware acceleration subsystem includes a first scheduler, a first hardware accelerator coupled to the first scheduler to process at least a first data element and a second data element, and a first load store engine coupled to the first hardware accelerator, the first load store engine configured to communicate with the first scheduler at a superblock level by sending a done signal to the first scheduler in response to determining that a block count is equal to a first BPR value and aggregate the first data element and the second data element based on the first BPR value to generate a first aggregated data element.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Niraj Nandan, Rajasekhar Reddy Allu, Brian Chae, Mihir Mody
  • Patent number: 11599975
    Abstract: An apparatus and method for geometrically correcting a distorted input frame and generating an undistorted output frame. The apparatus includes an external memory block that stores the input frame, a counter block to compute output coordinates of the output frame for a region based on a block size of the region, a back mapping block to generate input coordinates corresponding to each of the output coordinates, a bounding module to compute input blocks corresponding to each of the input coordinates, a buffer module to fetch data corresponding to each of the input blocks, an interpolation module to interpolate data from the buffer module and a display module that receives the interpolated data for each of the regions and stitch an output image. The method includes determining the size of the output block based on a magnification data.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: March 7, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Rajasekhar Reddy Allu, Niraj Nandan, Mihir Narendra Mody, Gang Hua, Brian Okchon Chae, Shashank Dabral, Hetul Sanghvi, Vikram VijayanBabu Appia, Sujith Shivalingappa
  • Patent number: 11537299
    Abstract: An integrated circuit includes: a local memory; and a first processing circuit coupled to the local memory. The first processing component is configured to: receive a first set of image data; perform a first image processing operation on the first set of image data to produce a second set of image data; and store at least some of the second set of image data into the local memory. The integrated circuit also includes a second processing circuit coupled to the local memory and configured to: receive at least some of the second set of image data from the local memory; and perform a second image processing operation on the second set of image data to produce a third set of image data.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 27, 2022
    Assignee: Texas Instmments Incorporated
    Inventors: Mihir Narendra Mody, Niraj Nandan, Rajasekhar Reddy Allu