Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.

Abstract: There is provided a wiring harness assembly comprising a main trunk cable assembly, a branch cable assembly and at least one connector. The main trunk assembly defines opposite terminal ends and comprises main trunk wires. The branch cable assembly defines opposite terminal ends and comprises branch wires. The connector connects the main trunk cable assembly and the branch cable assembly. The connector comprises an outer housing with an inner wiring harness positioned therein. The wiring harness comprises main trunk wire segments and branch wire segments interconnected at mutual connecting points. The main trunk wire segments define terminal ends connected to the main trunk wires at one of the terminal ends of the main trunk cable assembly. The branch wire segments define terminal ends connected to the branch wires at one of the terminal ends of the branch cable assembly.

Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

Abstract: Methods, systems, and devices for wireless communications are described. Aspects of the disclosure relate to enhanced load reporting between network entities (e.g., provided by a distributed unit (DU) to a centralized unit (CU) or by a CU to another CU). In some examples, the CU may provide one or more triggering events which may be used by the DU (or a second CU) to trigger the provisioning of a load report to the CU. Accordingly, the DU (or second CU) may be able to initiate a load report without relying on periodic reporting criteria. In some examples, the DU may initiate a load report to the CU without being configured with triggering events. In some examples, a DU may report measurements made associated with a communications load involving communications with both a parent network entity (e.g., a CU) and at least one child network entity (e.g., a user equipment).

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit an update to a previously reported set of UE artificial intelligence (AI) or machine learning (ML) capabilities. The UE may receive a configuration associated with performance of UE AI or ML operations based at least in part on the update. Numerous other aspects are described.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine one or more candidate base stations for a handover procedure for the UE. The UE may transmit an indication of the one or more candidate base stations to a serving base station. Numerous other aspects are provided.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.

Abstract: Various examples are directed to systems and methods for executing an enterprise resource planning solution using a database management system (DBMS). An order-to-cash process executing at the at least one processor accesses an indication of waste material for disposal and generates a waste disposal order, where the waste disposal order comprises a material description field including a description of the waste material, regulatory reporting data describing at least one report of the waste material to be provided to a regulatory agency, and a price field indicating a negative price.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: Methods, systems, and devices for wireless communications are described. A wireless device may receive an indication of a configuration for sensing measurement parameter reporting from a base station. The sensing measurement parameter reporting may be for a sensing operation. The wireless device may perform the sensing operation and transmit an indication of a measurement parameter value to the base station. The sensing measurement parameter value may be associated with a location of the wireless device. In some examples, the wireless device may transmit the indication of the sensing measurement parameter value based on performing the sensing operation.

Abstract: A method of wireless communication at a user equipment (UE), including: generating a first set of frequencies to search for signals from at least one candidate cell from which the UE may receive wireless service with respect to a first subscriber identity module (SIM); generating a second set of frequencies to search for signals from the at least one candidate cell from which the UE may receive wireless service with respect to the first SIM; scanning for one or more signals from the at least one candidate cell including tuning a first transceiver configured to operate in accordance with the first SIM to one or more of the first set frequencies; and scanning for one or more signals from the at least one candidate cell including tuning a second transceiver configured to operate in accordance with a second SIM to one or more of the second set of frequencies.

Abstract: Certain aspects of the present disclosure provide techniques for merging pages in communications systems using carrier aggregation (CA) or secondary component carriers (SCCs). An example method that may be performed by a user equipment (UE) includes: operating in a connected mode using a default data subscription (DDS) associated with a primary cell (PCell); detecting one or more secondary cells (SCells) associated with the DDS are configured for operating in the connected mode; and decoding one or more paging messages using at least a secondary component carrier (SCC) associated with a first SCell of the one or more SCells.

Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit capability information that indicates support for one or more model combinations of machine learning (ML) models, wherein the capability information further indicates one or more performance parameters of an ML model of the ML models with respect to a model combination of the one or more model combinations that includes the ML model. The UE may receive one or more indications to use one or more of the ML models based at least in part on the capability information. Numerous other aspects are described.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.

Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

Abstract: The present disclosure involves systems, software, and computer implemented methods for a remittance system that pre-populates remittance data based on historical usage of remittance transactions. One example system includes operations to generate, using a predictive model, data indicating a predicted likelihood of a user selecting at least one data exchange transaction, wherein the data indicates the predicted likelihood of the user performing the at least one data exchange transaction. A request is received to access a remittance page. In response, the at least one data exchange transaction that was previously generated is selected from a repository of predicted likelihoods. Remittance data associated with a UI element is generated that includes the at least one data exchange transaction. The remittance data is transmitted to the device. An indication from the device is received for interacting with the UI element. The data exchange transaction is executed in response to receiving the indication.

Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.