Patents by Inventor Rajen S. Sidhu

Rajen S. Sidhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651108
    Abstract: Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Zhizhong Tang, Syadwad Jain, Wei Hu, Michael A. Schroeder, Rajen S. Sidhu, Carl L. Deppisch, Patrick Nardi, Kelly P. Lofgreen, Manish Dubey
  • Publication number: 20180236609
    Abstract: Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 23, 2018
    Inventors: Rajen S. SIDHU, Martha A. DUDEK, James C. MATAYABAS, JR., Michelle S. PHEN-GIVONI, Wei TAN
  • Patent number: 10049971
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9950393
    Abstract: Flux formulations and solder attachment during the fabrication of electronic device assemblies are described. One flux formation includes a flux component and a metal particle component, the metal particle component being present in an amount of from 5 to 35 volume percent of the flux formulation. In one feature of certain embodiments, the metal particle component includes solder particles. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 24, 2018
    Assignee: INTEL CORPORATION
    Inventors: Rajen S. Sidhu, Martha A. Dudek, James C. Matayabas, Jr., Michelle S. Phen, Wei Tan
  • Publication number: 20180005917
    Abstract: Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Zhizhong Tang, Syadwad Jain, Wei Hu, Michael A. Schroeder, Rajen S. Sidhu, Carl L. Deppisch, Patrick Nardi, Kelly P. Lofgreen
  • Publication number: 20170207152
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9613933
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jr., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9461014
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
  • Publication number: 20160260679
    Abstract: Apparatuses, processes, and systems related to an interconnect with an increased z-height and decreased reflow temperature are described herein. In embodiments, an interconnect may include a solder ball and a solder paste to couple the solder ball to a substrate. The solder ball and/or solder paste may be comprised of an alloy with a relatively low melting point and an alloy with a relatively high melting point.
    Type: Application
    Filed: March 27, 2014
    Publication date: September 8, 2016
    Applicant: Intel Corporation
    Inventors: Kabirkumar J. Mirpuri, Hongjin Jiang, Tyler N. Osborn, Rajen S. Sidhu, Ibrahim Bekar, Susheel G. Jadhav
  • Patent number: 9394619
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Mukul P. Renavikar, Sandeep B. Sane
  • Patent number: 9283641
    Abstract: Embodiments of the present disclosure are directed towards flux materials for heated solder placement and associated techniques and configurations. In one embodiment, a method includes depositing a flux material on one or more pads of a package substrate, the flux material including a rosin material and a thixotropic agent and depositing one or more solder balls on the flux material disposed on the one or more pads, wherein depositing the one or more solder balls on the flux material is performed at a temperature greater than 80° C., and wherein the rosin material and the thixotropic agent are configured to resist softening at the temperature greater than 80° C. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: March 15, 2016
    Assignee: INTEL CORPORATION
    Inventors: Rajen S. Sidhu, Martha A. Dudek, Wei Tan
  • Patent number: 9257405
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek
  • Publication number: 20150255415
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, JR., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Publication number: 20150221609
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.
    Type: Application
    Filed: April 14, 2015
    Publication date: August 6, 2015
    Applicant: Intel Corporation
    Inventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
  • Patent number: 9064971
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
  • Patent number: 9024453
    Abstract: Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package to be tailored, for example based on function. Functional package interconnects may vary one of more of at least material layer composition, layer thickness, number of layers, or a number of materials to achieve a particular function, for example based on an application of the component(s) interconnected or an application of the assembly as a whole. In embodiments, parameters of the multi-layered laminated structures are varied dependent on the interconnect location within an area of a substrate, for example with structures having higher ductility at interconnect locations subject to higher stress.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Ashay A. Dani, Martha A. Dudek
  • Patent number: 8920934
    Abstract: Hybrid solder for solder balls and filled paste are described. A solder ball may be formed of a droplet of higher temperature solder and a coating of lower temperature solder. This may be used with a solder paste that has an adhesive and a filler of low temperature solder particles, the filler comprising less than 80 weight percent of the paste. The solder balls and paste may be used in soldering packages for microelectronic devices. A package may be formed by applying a solder paste to a bond pad of a substrate, attaching a hybrid solder ball to each pad using the paste, and attaching the package substrate to a microelectronic substrate by reflowing the hybrid solder balls to form a hybrid solder interconnect.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Hongjin Jiang, Arun Kumar C. Nallani, Rajen S. Sidhu, Martha A. Dudek, Weihua Tang
  • Patent number: 8896110
    Abstract: Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Wei Hu, Zhizhong Tang, Syadwad Jain, Rajen S. Sidhu
  • Patent number: 8895365
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Suriyakala Ramalingam, Rajen S. Sidhu, Nisha Ananthakrishnan, Sivakumar Nagarajan, Wei Tan, Sandeep Razdan, Vipul V. Mehta
  • Publication number: 20140319682
    Abstract: Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Rajen S. Sidhu, Wei Hu, Carl L. Deppisch, Martha A. Dudek