Patents by Inventor Rakesh Balakrishnan

Rakesh Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11537303
    Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. The data storage device can guide a host device to select a particular zone to open in zone namespace (ZNS) systems where the host device selects which zone to open. The data storage device tracks the workload of the various storage locations and create zones. The data storage device then provides selected zones having the least used storage locations with the idea of guiding the host device to select the zone having the least used storage locations. Thus, rather than utilizing a randomly selected unopened zone, the host will select, based upon guidance from the data storage device, zones that contain the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Rakesh Balakrishnan, Eldhose Peter, Judah Gamliel Hahn
  • Patent number: 11537305
    Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. When receiving a zone open command in a zone namespace (ZNS) system, rather than randomly selecting an unopen zone, zones may be categorized based upon storage location workload so that any new zone that is opened utilizes the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: December 27, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Rakesh Balakrishnan, Eldhose Peter, Judah Gamliel Hahn
  • Publication number: 20220391115
    Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. The data storage device can guide a host device to select a particular zone to open in zone namespace (ZNS) systems where the host device selects which zone to open. The data storage device tracks the workload of the various storage locations and create zones. The data storage device then provides selected zones having the least used storage locations with the idea of guiding the host device to select the zone having the least used storage locations. Thus, rather than utilizing a randomly selected unopened zone, the host will select, based upon guidance from the data storage device, zones that contain the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 8, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan MUTHIAH, Rakesh BALAKRISHNAN, Eldhose PETER, Judah Gamliel HAHN
  • Publication number: 20220391089
    Abstract: The present disclosure generally relates to creating new zones in a data storage device in a manner that ensures substantially even workload of the memory device storage locations. When receiving a zone open command in a zone namespace (ZNS) system, rather than randomly selecting an unopen zone, zones may be categorized based upon storage location workload so that any new zone that is opened utilizes the least utilized storage location. In so doing, generally even workload of the memory device storage locations is achieved.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 8, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan MUTHIAH, Rakesh BALAKRISHNAN, Eldhose PETER, Judah Gamliel HAHN
  • Publication number: 20220321975
    Abstract: A data storage device comprises a non-volatile memory, a buffer, and a controller. The controller is configured to decode a media file to extract timestamp information related to a set of frames of the media file and receive, from a host, a seek command associated with playback of the media file. The seek command includes a seek interval. The controller is further configured to remove at least a portion of the set of frames based at least in part on the seek interval and the extracted timestamp information and transmit a subset of the set of frames, not including the removed at least a portion of the set of frames, to the host.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 6, 2022
    Inventors: Eldhose PETER, Rakesh BALAKRISHNAN, Ruchir SINHA, Govind Kumar MANGAL
  • Patent number: 11461260
    Abstract: A memory card has a plurality of pads including a first set of pads located to connect with host contacts arranged in a first configuration for communication according to the micro Secure Digital (microSD) standard, a second set of pads located to connect with host contacts arranged in a second configuration for communication according to the Peripheral Component Interface express (PCIe) protocol, and a third set of pads located to connect with host contacts arranged in a third configuration for communication according to the Universal Flash Storage (UFS) standard. The plurality of pads includes one or more common pads that are common to the second set of pads and the third set of pads.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: October 4, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yoseph Pinto, Shiva K, Eldhose Peter, Rakesh Balakrishnan
  • Publication number: 20220308798
    Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 29, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav
  • Patent number: 11442665
    Abstract: A storage system and method for dynamic selection of a host interface are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a selection of a first host interface; in response to receiving the selection of the first host interface, implement the first host interface; after the first host interface has been implemented, receive, from the host, a selection of a second host interface; and in response to receiving the selection of the second host interface, implement the second host interface even though the first host interface was previously implemented. Other embodiments are provided.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: September 13, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Shiva K
  • Publication number: 20220285977
    Abstract: A microgrid includes a power system configured to output system power and an automatic transfer switch (ATS). The ATS includes a normal terminal that is electrically connected to a grid power line configured to receive grid power from a power utility, an emergency terminal that is electrically connected to a system power line configured to receive system power from the power system, and a load terminal that is electrically connected to a critical load line configured to provide power to a critical load. The microgrid also includes a bypass line electrically connected to the system power line and the critical load line, so as to bypass the ATS, and a circuit breaker configured to control power flow through the bypass line.
    Type: Application
    Filed: March 4, 2022
    Publication date: September 8, 2022
    Inventors: Prasad PMSVVSV, Mehdi EBAD, Ranganathan GURUNATHAN, Vishal Anand GOPALAKRISHNAN, Jayanth MOODLIAR, Saravana NARAYANASAMY, Rakesh Kumar ROY, Deepak BALAKRISHNAN
  • Publication number: 20220269629
    Abstract: A memory card has a plurality of pads including a first set of pads located to connect with host contacts arranged in a first configuration for communication according to the micro Secure Digital (microSD) standard, a second set of pads located to connect with host contacts arranged in a second configuration for communication according to the Peripheral Component Interface express (PCIe) protocol, and a third set of pads located to connect with host contacts arranged in a third configuration for communication according to the Universal Flash Storage (UFS) standard. The plurality of pads includes one or more common pads that are common to the second set of pads and the third set of pads.
    Type: Application
    Filed: February 19, 2021
    Publication date: August 25, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yoseph Pinto, Shiva K, Eldhose Peter, Rakesh Balakrishnan
  • Publication number: 20220229789
    Abstract: A Host Memory Buffer (HMB) Abstraction Protocol layer is individually included in a host device and a SD-PCIe device. The HMB Abstraction Protocol layers provide the SD-PCIe device access to a HMB region of the host device when the SD-PCIe is operating in the SD mode, where the HMB region was previously inaccessible to the SD-PCIe device when operating in the SD mode.
    Type: Application
    Filed: February 22, 2021
    Publication date: July 21, 2022
    Inventors: Rakesh Balakrishnan, Yuvaraj Kumar, Chandramani
  • Patent number: 11392327
    Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: July 19, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav
  • Publication number: 20220206711
    Abstract: Systems and methods are disclosed for providing multilingual media files. In certain embodiments, a data storage device includes a controller configured to: receive a command to write data for a media file to a non-volatile memory, wherein the media file includes one or more frames each including a video frame and a plurality of audio frames associated with a plurality of languages; decode using a decoder a first frame of the media file to determine a logical block address (LBA) for a video frame of the first frame and an LBA for each of a plurality of audio frames of the first frame; write the first frame to the non-volatile memory; and update a logical-to-physical (L2P) table to add information associated with the LBA for the video frame of the first frame and the LBA for each of the plurality of audio frames of the first frame.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 30, 2022
    Inventors: Rakesh Balakrishnan, Govind Mangal, Eldhose Peter
  • Publication number: 20220210521
    Abstract: A data storage device comprises a non-volatile memory, a buffer, and a controller. The controller is configured to decode a media file to extract timestamp information related to a set of frames of the media file and receive, from a host, a seek command associated with playback of the media file. The seek command includes a seek interval. The controller is further configured to remove at least a portion of the set of frames based at least in part on the seek interval and the extracted timestamp information and transmit a subset of the set of frames, not including the removed at least a portion of the set of frames, to the host.
    Type: Application
    Filed: February 26, 2021
    Publication date: June 30, 2022
    Inventors: Eldhose PETER, Rakesh BALAKRISHNAN, Ruchir SINHA, Govind Kumar MANGAL
  • Patent number: 11375286
    Abstract: A data storage device comprises a non-volatile memory, a buffer, and a controller. The controller is configured to decode a media file to extract timestamp information related to a set of frames of the media file and receive, from a host, a seek command associated with playback of the media file. The seek command includes a seek interval. The controller is further configured to remove at least a portion of the set of frames based at least in part on the seek interval and the extracted timestamp information and transmit a subset of the set of frames, not including the removed at least a portion of the set of frames, to the host.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 28, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eldhose Peter, Rakesh Balakrishnan, Ruchir Sinha, Govind Kumar Mangal
  • Publication number: 20220188151
    Abstract: A non-volatile storage system includes a memory controller and multiple integrated memory assemblies separate from and in communication with the memory controller. The integrated memory assemblies each comprises a memory die and a control die. The control die is connected (e.g., bonded) to the memory die. The memory controller and the control die include separate compute resources (e.g., each includes a processor). The storage system is configured to receive a request to perform a compute task and assign that compute task to any one or more of the memory controller and the integrated memory assemblies based on anticipated amount of data to be transferred to or from non-volatile memory for the compute task, computational resource need of the compute task, and/or available bandwidth of the memory controller and the control dies.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 16, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Rakesh Balakrishnan
  • Publication number: 20220179586
    Abstract: A storage system and method for dynamic selection of a host interface are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a selection of a first host interface; in response to receiving the selection of the first host interface, implement the first host interface; after the first host interface has been implemented, receive, from the host, a selection of a second host interface; and in response to receiving the selection of the second host interface, implement the second host interface even though the first host interface was previously implemented. Other embodiments are provided.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 9, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Shiva K
  • Publication number: 20220129388
    Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller receives commands from a host, performs logical address to physical address translation (“address translation”) operations for the commands, and instructs the integrated memory assembly to perform one or more operations in support of the command. The control die also includes the ability to perform the address translation. When performing a command from the host, the memory controller can choose to perform the necessary address translation or instruct the control die to perform the address translation. When the control die performs the address translation, the resulting physical address is used by the control die to perform one or more operations in support of the command.
    Type: Application
    Filed: February 17, 2021
    Publication date: April 28, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav, Ramanathan Muthiah, Vimal Kumar Jain
  • Patent number: 11281399
    Abstract: A dual-interface storage system and method for use therewith are provided. In one embodiment, the storage system comprises a memory; a connector compatible with both a first host interface and a second host interface; a first data path to at least a part of the memory comprising the first host interface and a controller for the first host interface; a second data path to at least another part of the memory comprising the second host interface and a controller for the second host interface; and a switch configured to connect the connector to either the first data path or the second data path in response to a command from a host. Other embodiments are disclosed.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: March 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shiva K, Eldhose Peter, Rakesh Balakrishnan
  • Publication number: 20220075559
    Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.
    Type: Application
    Filed: February 17, 2021
    Publication date: March 10, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav