Patents by Inventor Ralf Illgen

Ralf Illgen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8536034
    Abstract: Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Thilo Scheiper, Jan Hoentschel
  • Publication number: 20130196495
    Abstract: A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 1, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Publication number: 20130181299
    Abstract: In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 18, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Publication number: 20130178024
    Abstract: Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 11, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Publication number: 20130175640
    Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the transistor includes a channel region at a surface of a semiconductor substrate. The method includes etching first recesses into the semiconductor substrate adjacent the channel region to define adjacent regions in the semiconductor substrate between the first recesses and the channel region. A first layer of SiGe is epitaxially grown in the first recesses. The method includes etching second recesses through the first layer of SiGe and into the adjacent regions of the semiconductor substrate. Further, a second layer of SiGe is epitaxially grown in the second recesses.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Illgen, Stefan Flachowsky
  • Patent number: 8476131
    Abstract: In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: July 2, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Thilo Scheiper, Ricardo P. Mikalo
  • Patent number: 8466018
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: June 18, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Illgen, Stefan Flachowsky, Ina Ostermay
  • Publication number: 20130069123
    Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming first doped stressor regions in a first region of semiconductor material, forming second doped stressor regions in a second region of semiconductor material after forming the first doped stressor regions, and after forming the second doped stressor regions, annealing the semiconductor device structure to activate ions of the first and second doped stressor regions concurrently. The amount of time for the annealing is chosen to inhibit diffusion of the ions of the first and second doped stressor regions.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf Illgen, Stefan Flachowsky, Ina Ostermay
  • Publication number: 20130049121
    Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
  • Publication number: 20130052782
    Abstract: Generally, the present disclosure is directed to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate. One illustrative method disclosed herein involves forming a gate insulation layer on a substrate, forming a layer of gate electrode material above the gate insulation material and performing an ion implantation process with a material comprising hydrogen or a hydrogen-containing compound to introduce the hydrogen or hydrogen-containing compound proximate an interface between the gate insulation layer and said substrate with a concentration of the implanted hydrogen or hydrogen-containing compound being at least 1e10 ions/cm2.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
  • Publication number: 20130052783
    Abstract: Disclosed herein are various methods of forming stressed silicon-carbon areas in an NMOS transistor device. In one example, a method disclosed herein includes forming a layer of amorphous carbon above a surface of a semiconducting substrate comprising a plurality of N-doped regions and performing an ion implantation process on the layer of amorphous carbon to dislodge carbon atoms from the layer of amorphous carbon and to drive the dislodged carbon atoms into the N-doped regions in the substrate.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Thilo Scheiper, Jan Hoentschel
  • Publication number: 20130049126
    Abstract: In one example, a method disclosed herein includes forming a gate electrode structure for a PMOS transistor and a gate electrode structure for a NMOS transistor, forming a plurality of cavities in the substrate proximate the gate electrode structure of the PMOS transistor and performing an epitaxial deposition process to form raised silicon-germanium regions is the cavities. The method concludes with the step of performing a common etching process on the PMOS transistor and the NMOS transistor to define recessed regions in the substrate proximate the gate electrode structure of the NMOS transistor and to reduce the amount of the silicon-germanium material positioned above the surface of the substrate for the PMOS transistor.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Ralf Illgen, Thilo Scheiper, Ricardo P. Mikalo
  • Publication number: 20130032877
    Abstract: When forming sophisticated semiconductor devices including high-k metal gate electrode structures and N-channel transistors, superior performance may be achieved by incorporating epitaxially grown semiconductor materials, for instance a strain-inducing silicon/carbon alloy in combination with an N-doped silicon material, which may provide an acceptable sheet resistivity.
    Type: Application
    Filed: July 16, 2012
    Publication date: February 7, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Ina OSTERMAY, Ralf ILLGEN, Stefan FLACHOWSKY
  • Publication number: 20130029463
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming extension implant regions in a PMOS region and a NMOS region of a semiconducting substrate for a PMOS device and a NMOS device, respectively and, after forming the extension implant regions, performing a first heating process. The method further includes forming a plurality of cavities in the PMOS region of the substrate, performing at least one epitaxial deposition process to form a plurality of in-situ doped semiconductor layers that are positioned in or above each of said cavities, and forming a masking layer that exposes the NMOS region and covers the PMOS region. The method concludes with the steps of forming source/drain implant regions in the NMOS region of the substrate for the NMOS device and performing a second heating process.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf Illgen, Stefan Flachowsky, Ina Ostermay
  • Patent number: 8338885
    Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained, in the adjacent channel region.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Thomas Feudel, Ralf Illgen
  • Publication number: 20120231591
    Abstract: Methods are provided for fabricating CMOS integrated circuits. In accordance with one embodiment the methods include forming a gate electrode structure overlying an N-doped portion of a semiconductor substrate and growing an embedded silicon germanium area in the N-doped portion in alignment with the gate electrode structure. A layer of silicon is selectively grown overlying the embedded silicon germanium area and a nickel silicide contact is made to the layer of silicon.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 13, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan FLACHOWSKY, Ralf ILLGEN, Ina OSTERMAY, Jan HOENTSCHEL
  • Publication number: 20120146155
    Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained, in the adjacent channel region.
    Type: Application
    Filed: February 22, 2012
    Publication date: June 14, 2012
    Inventors: Jan Hoentschel, Thomas Feudel, Ralf Illgen
  • Patent number: 8143133
    Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: March 27, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Thomas Feudel, Ralf Illgen
  • Publication number: 20110121398
    Abstract: During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a strain-inducing area within a sidewall spacer structure. Due to the corresponding void formation in the spacer structure, a high tensile strain component may be obtained in the adjacent channel region.
    Type: Application
    Filed: November 23, 2009
    Publication date: May 26, 2011
    Inventors: Jan Hoentschel, Thomas Feudel, Ralf Illgen