Abstract: A logic array includes an AND plane, a first OR plane, and a second OR plane. The AND plane is adapted to receive a plurality of logic array inputs and provide a plurality of minterms. Each minterm represents a logical combination of a subset of the plurality of logic array inputs. The first OR plane is adapted to receive the minterms and provide a plurality of intermediate outputs. Each intermediate output represents a logical combination of a subset of the minterms. The second OR plane is adapted to receive the intermediate outputs and provide a plurality of logic array outputs. Each logic array output represents a logical combination of a subset of the intermediate outputs. A method for programming a logic array includes providing a plurality of minterms. A plurality of subsets of the minterms are logically combined to define a plurality of intermediate outputs. A plurality of subsets of the intermediate outputs are logically combined to define a plurality of logic array outputs.

Abstract: The present invention provides a PLA structure having logic interposed between an AND plane and an OR plane, wherein the interposed logic provides an additional set of minterms to the OR plane such that any PLA output function can be implemented with substantially fewer input signals. In this way, parasitic loading for implementation of any particular logic function is reduced.

Abstract: A logic array includes a first logic plane, a second logic plane, and a third logic plane. The first logic plane has a first plurality of intermediate outputs, and the second logic plane has a second plurality of intermediate outputs. The third logic plane has first and second opposing sides and is adapted to receive the first and second pluralities of intermediate outputs. The first plurality of intermediate outputs intersect the third logic plane through the first side, and the second plurality of intermediate outputs intersect the third logic plane through the second side. A method for increasing the density of a logic array includes providing a first logic plane, a second logic plane, and a third logic plane. The first logic plane has a first plurality of intermediate outputs, and the second logic plane has a second plurality of intermediate outputs. The first plurality of intermediate outputs and the second plurality of intermediate outputs are interleaved in the third logic plane.

Abstract: A method for creating an output vector Z(n-1:0) from a first vector X(n-1:0) and a second vector Y(n-1:0). The second vector Y(n-1:0) is a complement of the first vector X(n-1:0). The method subdivides X into a lower-order subvector XL(m-1:0) and a higher-order subvector XH(n-1:m). If a first 1 exists in position k in XL, then Z(k) is set to 0 and all other bits in Z(m-1:0) are set to 1. If a first 1 does not exist in XL, then all bits in Z(m-1:0) are set to 1. The method also determines if a 1 exists in XL. If a 1 exists in XL, then Z(n-1:m) is masked.