Patents by Inventor Ramakanth Alapati

Ramakanth Alapati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9711662
    Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming an upper interlayer dielectric overlying an optical modulator and a photodetector, where the photodetector has a shoulder and a plug. An etch stop is formed overlying the upper interlayer dielectric. The etch stop is a first, second, and third distance from an uppermost surface of the optical modulator, the shoulder, and the plug, respectively, where the first, second, and third distances are all different from each other. A first, second, and third contact are formed through the upper interlayer dielectric, where the first, second and third contacts are in electrical communication with the optical modulator, the shoulder, and the plug, respectively.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shunqiang Gong, Benfu Lin, Juan Boon Tan, Ramakanth Alapati
  • Publication number: 20170062399
    Abstract: Methods for removing low-k dielectric material from dicing lanes in a bonded pair of IC wafers and the resulting device are disclosed. Embodiments include providing low-k dielectric and standard dielectric layers on upper surfaces of top and bottom IC substrates, each including an array of adjacent IC die areas separated by dicing lanes; removing from the dicing lanes the standard and low-k dielectric layers to form cavities exposing sections of the upper surfaces of IC substrates; depositing a standard dielectric material in the cavities and on upper surfaces of the standard dielectric layer of the top and bottom IC substrates; planarizing upper surfaces of the standard dielectric material of the IC substrates; forming a face-to-face bonding of the IC substrates, wherein the dicing lanes in the IC substrates are vertically aligned; and dicing adjacent bonded IC die areas through vertically aligned dicing lanes in the IC substrates.
    Type: Application
    Filed: August 24, 2015
    Publication date: March 2, 2017
    Inventors: Luke ENGLAND, Ramakanth ALAPATI
  • Publication number: 20170054039
    Abstract: Device and a method of forming a device are disclosed. The method includes providing a substrate. The substrate includes a buried oxide (BOX) layer having an initial thickness TB1 sandwiched in between a top surface layer and a base substrate. The top surface layer is processed to form one or more photonic devices and first and second isolation regions. An interlevel dielectric (ILD) layer is formed on the substrate. Through dielectric via (TDV) contacts extending from a top surface of the dielectric ILD layer to within the BOX layer of the substrate are formed. Lower and upper interconnect levels are formed on the ILD layer. A carrier substrate is provided over a top surface of the upper interconnect levels. The base substrate and a portion of the BOX layer are removed to expose a bottom surface of the TDV contacts.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 23, 2017
    Inventors: Shunqiang GONG, Juan Boon TAN, Ramakanth ALAPATI
  • Patent number: 9553080
    Abstract: Methods for integrating MOL TSVs in 3D SoC devices including face-to-face bonded IC chips. Embodiments include providing a device layer in each of IC chips on upper surfaces of top and bottom silicon wafers; forming, subsequent to the device layer, through-silicon vias (TSVs) extending through an upper surface of the device layer in each of the IC chips and into the bottom Si wafer; forming, subsequent to the TSVs, a dielectric layer on the upper surface of the device layer in each of the IC chips of the top and bottom Si wafers; forming a back-end-of-line metal layer in the dielectric layer of each of the IC chips of the top and bottom Si wafers; face-to-face bonding of opposing IC chips of the top and bottom Si wafers; and dicing adjacent bonded IC chips through vertically aligned dicing lanes in the top and bottom Si wafers.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke England, Ramakanth Alapati
  • Publication number: 20160165729
    Abstract: A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 9, 2016
    Inventors: Saket CHADDA, Ramakanth ALAPATI, Adam BEECE
  • Patent number: 9318466
    Abstract: A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 19, 2016
    Assignee: GlobalFoundries Inc.
    Inventors: Saket Chadda, Ramakanth Alapati, Adam Beece
  • Publication number: 20160064354
    Abstract: A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventors: Saket CHADDA, Ramakanth ALAPATI, Adam BEECE
  • Patent number: 9184159
    Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 10, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
  • Patent number: 9123787
    Abstract: Exemplary embodiments of the present invention provide a V0 via unit cell with multiple keep out zones. The keep out zones are oriented concentrically and provide support for multiple sizes of through-silicon vias (TSVs). An off-center alignment between the V0 via unit cell and a probe pad is used to improve contact between the V0 vias and a probe pad. During a chip redesign, the TSV size may be changed without the need to revise the V0 mask.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: September 1, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Himani S. Kamineni, Ramakanth Alapati, Maria Balicka
  • Publication number: 20150076706
    Abstract: Exemplary embodiments of the present invention provide a V0 via unit cell with multiple keep out zones. The keep out zones are oriented concentrically and provide support for multiple sizes of through-silicon vias (TSVs). An off-center alignment between the V0 via unit cell and a probe pad is used to improve contact between the V0 vias and a probe pad. During a chip redesign, the TSV size may be changed without the need to revise the V0 mask.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Applicant: GLOBAL FOUNDRIES Inc.
    Inventors: Himani S. Kamineni, Ramakanth Alapati, Maria Balicka
  • Patent number: 8809198
    Abstract: A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: August 19, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ramakanth Alapati, Paul Morgan, Max Hineman
  • Publication number: 20140070405
    Abstract: One illustrative device disclosed herein includes a device substrate having a plurality of first die formed adjacent a front side of the device substrate, a glass window wafer attached to a back side of the device substrate, wherein the glass window wafer has a plurality of openings formed therein and a coefficient of thermal expansion that is within plus or minus 200-500% of the coefficient of thermal expansion of the device wafer, and a plurality of second die, each of which is positioned in one of the openings in the glass window wafer and electrically coupled to one of the first die.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Rahul Agarwal, Ramakanth Alapati
  • Patent number: 8669166
    Abstract: One illustrative method disclosed herein includes forming a plurality of die above a crystalline semiconducting substrate, irradiating and cooling an edge region of the substrate to form an amorphous region in the edge region of the substrate and, after forming the amorphous region, performing at least one process operation to reduce the thickness of the substrate.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: March 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Rahul Agarwal, Ramakanth Alapati, Jon Greenwood
  • Publication number: 20140051233
    Abstract: One illustrative method disclosed herein includes forming a plurality of die above a crystalline semiconducting substrate, irradiating and cooling an edge region of the substrate to form an amorphous region in the edge region of the substrate and, after forming the amorphous region, performing at least one process operation to reduce the thickness of the substrate.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Rahul Agarwal, Ramakanth Alapati, Jon Greenwood
  • Patent number: 8637993
    Abstract: A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: January 28, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Chun Yu Wong, Ramakanth Alapati, Teck Jung Tang
  • Patent number: 8598632
    Abstract: An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: December 3, 2013
    Assignee: Round Rock Research LLC
    Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
  • Patent number: 8598043
    Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: December 3, 2013
    Assignee: Micron Technology Inc.
    Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu, Luan C. Tran
  • Publication number: 20130277854
    Abstract: A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.
    Type: Application
    Filed: April 23, 2012
    Publication date: October 24, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Chun Yu Wong, Ramakanth Alapati, Teck Jung Tang
  • Patent number: 8431456
    Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 30, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu
  • Patent number: 8338959
    Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: December 25, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati