Patents by Inventor Ramesh Narayanaswamy
Ramesh Narayanaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240406493Abstract: A method, a non-transitory computer readable medium, and set-top box with Android with fast channel change on a set-top box with Android are disclosed. The method includes: playing, on the set-top box, a first channel with android.media.tv.tvView.tune; and prefetching and dropping, from a memory of the set-top box, one or more additional channels with an appPrivateCommand with bundle parameters.Type: ApplicationFiled: October 28, 2021Publication date: December 5, 2024Applicant: ARRIS ENTERPRISES LLCInventors: Hongbin ZHAO, Kanaka LAKSHMI, Ramesh NARAYANASWAMY
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Patent number: 12153864Abstract: This disclosure describes an apparatus and method for simulating circuit designs. An apparatus for simulating circuit designs includes a first simulation vector processor (SVP) and a second SVP communicatively coupled to the first SVP. The first SVP simulates a first portion of a circuit design under test. The second SVP simulates the first portion of the circuit design under test at least partially while the first SVP simulates the first portion of the circuit design and asynchronously with the first SVP and transmits data to the first SVP while simulating the first portion of the circuit design, wherein the first SVP uses the data while simulating the first portion of the circuit design.Type: GrantFiled: February 9, 2022Date of Patent: November 26, 2024Assignee: Synopsys, Inc.Inventors: Subramanian Ganesan, Ramesh Narayanaswamy, Dinesh Madusanke Pasikku Hannadige, Chanaka Ranathunga, Aditha Pabasara Rajakaruna, Subha Sankar Chowdhury
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Publication number: 20240323469Abstract: An exemplary system provides dynamic supplemental content in a recorded content playback. The supplemental content are dynamically added to the recorded playback content which was streamed over IP using a MPEG-DASH format or related format. This allows a service provider to provide pertinent supplemental content to the end user and service provider.Type: ApplicationFiled: February 15, 2022Publication date: September 26, 2024Inventors: Ramesh NARAYANASWAMY, Sandeep Guddekoppa SURESH
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Publication number: 20230403442Abstract: A companion device for use with a server device, a media device and a display device, the server device having stored therein a metadata manifest including metadata and time data associated with content and being configured to transmit the metadata manifest, the media device being configured to provide the content and content timing information to the display device, the display device being configured to display media, the content timing information being additionally associated with the time data, the companion device comprising: a memory having instructions stored therein; and a processor configured to execute the instructions stored in the memory to cause the companion device to: receive the content timing information from the media device; transmit a manifest request to the server device based on the content timing information; receive the metadata manifest from the server device; and instruct the display to display an icon based on the metadata.Type: ApplicationFiled: May 31, 2023Publication date: December 14, 2023Applicant: ARRIS Enterprises LLCInventors: Ramesh NARAYANASWAMY, Anand Madhav Rao HALLUR, Sandeep Guddekoppa SURESH, Krishna Prasad PANJE
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Publication number: 20230025563Abstract: A method, a non-transitory computer readable medium, and a system are disclosed for synchronized playback controls for viewing of video content. The method includes connecting, to a synchronization service, a plurality of media consumption devices; receiving, on the synchronization service, a control request from one or more of the plurality of media consumption devices; and sending, from the synchronization service, a control signal to each of the plurality of media consumption devices to implement a playback control to synchronize a playback of the video content in each of the plurality of media consumption devices.Type: ApplicationFiled: May 5, 2022Publication date: January 26, 2023Applicant: ARRIS Enterprises LLCInventors: Ramesh NARAYANASWAMY, Praveen GIRISH
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Publication number: 20230020848Abstract: A method, a non-transitory computer readable medium, and a system are disclosed for advertisement on demand. The method includes uploading, on a cloud server, media content with embedded advertisement on demand content; forwarding, from the cloud server, the media content with the embedded advertisement on demand content to a media consumption device; receiving, on the cloud server, a request for the embedded advertisement on demand content from the media consumption device; and forwarding, from the cloud server, information on the requested embedded advertisement to the media consumption device.Type: ApplicationFiled: May 3, 2022Publication date: January 19, 2023Applicant: ARRIS Enterprises LLCInventors: Ramesh NARAYANASWAMY, Anand Madhav Rao HALLUR
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Publication number: 20220394074Abstract: A system and method enabling the storage and retrieval of packetized digital content data in a manner which minimizes the detrimental effects of dropped data packets. The dropped packets, encoded in accordance with a first profile, are detected and corresponding data packets obtained from an alternate profile of the digital content are substituted for the missing packets when the data is retrieved. Upon retrieval, the stored data packets are decoded in accordance with protocols associated with the particular profile from which each stored packet was obtained.Type: ApplicationFiled: June 1, 2022Publication date: December 8, 2022Applicant: ARRIS ENTERPRISES LLCInventors: Ramesh Narayanaswamy, Sandeep Guddekoppa Suresh
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Publication number: 20220253583Abstract: This disclosure describes an apparatus and method for simulating circuit designs. An apparatus for simulating circuit designs includes a first simulation vector processor (SVP) and a second SVP communicatively coupled to the first SVP. The first SVP simulates a first portion of a circuit design under test. The second SVP simulates the first portion of the circuit design under test at least partially while the first SVP simulates the first portion of the circuit design and asynchronously with the first SVP and transmits data to the first SVP while simulating the first portion of the circuit design, wherein the first SVP uses the data while simulating the first portion of the circuit design.Type: ApplicationFiled: February 9, 2022Publication date: August 11, 2022Inventors: Subramanian GANESAN, Ramesh NARAYANASWAMY, Dinesh Madusanke PASIKKU HANNADIGE, Chanaka RANATHUNGA, Aditha Pabasara RAJAKARUNA, Subha Sankar CHOWDHURY
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Publication number: 20220198120Abstract: A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of the plurality of values having one of four states. The evaluation further includes operation circuitry that receives the plurality of values and the control signals, performs one or more operations of the circuit design with the plurality of values based on the control signals, and outputs operation values based on performing the one or more operations, the operation values indicative of an error within the circuit design.Type: ApplicationFiled: December 17, 2021Publication date: June 23, 2022Inventors: Ramesh NARAYANASWAMY, Subramanian GANESAN, Dinesh Madusanke PASIKKU HANNADIGE
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Patent number: 10853544Abstract: Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.Type: GrantFiled: March 13, 2017Date of Patent: December 1, 2020Assignee: SYNOPSYS, INC.Inventors: Ramesh Narayanaswamy, Paraminder S. Sahai, Chiahon Chien
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Patent number: 10423740Abstract: Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.Type: GrantFiled: April 29, 2009Date of Patent: September 24, 2019Assignee: SYNOPSYS, INC.Inventors: Alexander Rabinovitch, Ramesh Narayanaswamy
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Publication number: 20170185700Abstract: Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Ramesh Narayanaswamy, Paraminder S. Sahai, Chiahon Chien
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Patent number: 9558306Abstract: An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that does not satisfy the target timing goal. A measure of slack is computed for each pipeline level in the identified pipeline region. Using the computed slack, path lengths of combinational regions in the pipeline levels of the identified pipeline region are iteratively retimed. The resulting circuit design is simulated using the retimed path lengths if the retimed critical path of the pipeline region satisfies the target timing goal.Type: GrantFiled: May 7, 2013Date of Patent: January 31, 2017Assignee: Synopsys, Inc.Inventors: Ramesh Narayanaswamy, Anil Nagori
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Patent number: 9507896Abstract: An approach for simulating an electronic circuit design uses the influence of a set of input changes of regions of the circuit design to schedule which levels within regions of a circuit should be simulated. The state of one or more inputs of one or more regions of the circuit design is checked to determine if inputs to these regions changed. For each input having an input change, a logic level depth associated with the input is computed. Using the computed logic levels, a maximum logic level depth of the one or more regions is computed for a set of input changes. Thus, for each region that has an input with a state indicating an input change, simulation may be scheduled for first logic level through and including the determined maximum logic level in each region of the circuit design in parallel.Type: GrantFiled: May 7, 2013Date of Patent: November 29, 2016Assignee: Synopsys, Inc.Inventors: Ramesh Narayanaswamy, Paraminder S. Sahai
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Publication number: 20130297279Abstract: An approach for simulating an electronic circuit design uses the influence of a set of input changes of regions of the circuit design to schedule which levels within regions of a circuit should be simulated. The state of one or more inputs of one or more regions of the circuit design is checked to determine if inputs to these regions changed. For each input having an input change, a logic level depth associated with the input is computed. Using the computed logic levels, a maximum logic level depth of the one or more regions is computed for a set of input changes. Thus, for each region that has an input with a state indicating an input change, simulation may be scheduled for first logic level through and including the determined maximum logic level in each region of the circuit design in parallel.Type: ApplicationFiled: May 7, 2013Publication date: November 7, 2013Applicant: Synopsys, Inc.Inventors: Ramesh Narayanaswamy, Paraminder S. Sahai
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Publication number: 20130297278Abstract: An approach for simulating a circuit design partitions the circuit design into pipeline regions that include one or more pipeline levels. A path length is computed for each combinational region within a pipeline region to compute an achievable timing goal for each pipeline region. A target retiming goal is determined for the set of pipeline regions based on the computed achievable timing goals of the pipeline regions. A pipeline region is identified from the set of pipeline regions that does not satisfy the target timing goal. A measure of slack is computed for each pipeline level in the identified pipeline region. Using the computed slack, path lengths of combinational regions in the pipeline levels of the identified pipeline region are iteratively retimed. The resulting circuit design is simulated using the retimed path lengths if the retimed critical path of the pipeline region satisfies the target timing goal.Type: ApplicationFiled: May 7, 2013Publication date: November 7, 2013Applicant: Synopsys, Inc.Inventors: Ramesh Narayanaswamy, Anil Nagori
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Publication number: 20130290919Abstract: Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.Type: ApplicationFiled: October 6, 2012Publication date: October 31, 2013Applicant: SYNOPSYS, INC.Inventors: Ramesh Narayanaswamy, Paraminder S. Sahai, Chiahon Chien
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Patent number: 8359186Abstract: An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.Type: GrantFiled: June 20, 2007Date of Patent: January 22, 2013Inventors: Subbu Ganesan, Ramesh Narayanaswamy, Ian Michael Nixon, Leonid Alexander Broukhis, Thomas Hanni Spencer
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Publication number: 20100280814Abstract: Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.Type: ApplicationFiled: April 29, 2009Publication date: November 4, 2010Applicant: SYNOPSYS, INC.Inventors: Alexander Rabinovitch, Ramesh Narayanaswamy
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Patent number: 7548842Abstract: A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.Type: GrantFiled: January 26, 2006Date of Patent: June 16, 2009Assignee: Eve S.A.Inventors: Subbu Ganesan, Leonid Alexander Broukhis, Ramesh Narayanaswamy, Ian Michael Nixon, Thomas Hanni Spencer