Abstract: Embodiments of the present disclosure generally relate to methods for forming a waveguide. Methods may include measuring a waveguide substrate, the waveguide having a substrate thickness distribution; and depositing an index-matched layer onto a surface of the waveguide, the index-matched layer having a first surface disposed on the waveguide substrate and a second surface opposing the first surface, wherein the index-matched layer is disposed only over a portion of the waveguide substrate, and a device slope of a second surface of the index-matched layer is substantially the same as the waveguide slope of the first surface of the waveguide.

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

Abstract: Embodiments of the present disclosure generally relate to imprint compositions and materials and related processes useful for nanoimprint lithography (NIL). In one or more embodiments, an imprint composition is provided and contains a plurality of passivated nanoparticles, one or more solvents, a surface ligand, an additive, and an acrylate. Each passivated nanoparticle contains a core and one or more shells, where the core contains one or more metal oxides and the shell contains one or more passivation materials. The passivation material of the shell contains one or more silicon-containing compounds.

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Abstract: An optical device coating assembly is provided. The optical device coating assembly includes a substrate support operable to retain an optical device substrate. The coating assembly further includes a first actuator connected to the substrate support. The first actuator is configured to rotate the substrate support. The coating assembly includes a holder configured to hold a coating applicator against an edge of the optical device substrate when the optical device substrate is rotated on the substrate support and a second actuator operable to apply a force on the holder in a direction towards the substrate support. The second actuator is a constant force actuator.

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

Abstract: Embodiments of the present disclosure generally relate to densified nanoimprint films and processes for making these densified nanoimprint films, as well as optical devices containing the densified nanoimprint films. In one or more embodiments, a densified nanoimprint film contains a base nanoimprint film and a metal oxide disposed on the base nanoimprint film and in between the nanoparticles. The base nanoimprint film contains nanoparticles, where the nanoparticles contain titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, hafnium oxide, chromium oxide, indium tin oxide, silicon nitride, or any combination thereof. The metal oxide contains aluminum oxide, titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, indium oxide, indium tin oxide, hafnium oxide, chromium oxide, scandium oxide, tin oxide, zinc oxide, yttrium oxide, praseodymium oxide, magnesium oxide, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

Abstract: Embodiments of the present disclosure generally relate to imprint compositions and materials and related processes useful for nanoimprint lithography (NIL). In one or more embodiments, an imprint composition is provided and contains a plurality of passivated nanoparticles, one or more solvents, a surface ligand, an additive, and an acrylate. Each passivated nanoparticle contains a core and one or more shells, where the core contains one or more metal oxides and the shell contains one or more passivation materials. The passivation material of the shell contains one or more atomic layer deposition (ALD) materials, one or more block copolymers, or one or more silicon-containing compounds.

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Abstract: A method of forming an optical device is provided. The method includes forming a first layer over a plurality of optical structures, the first layer including a first plurality of nanoparticles and a second plurality of nanoparticles. The first plurality of nanoparticles and the second plurality of nanoparticles are formed of a first material, the first plurality of nanoparticles have a first average volume, greater than 95% of the first plurality of nanoparticles have a volume within 10% of the first average volume, the second plurality of nanoparticles have a second average volume, greater than 95% of the second plurality of nanoparticles have a volume within 10% of the second average volume, and the second average volume is at least 25% larger the first average volume.

Abstract: An optical device coating assembly is provided. The optical device coating assembly includes a substrate support operable to retain an optical device substrate. The coating assembly further includes a first actuator connected to the substrate support. The first actuator is configured to rotate the substrate support. The coating assembly includes a holder configured to hold a coating applicator against an edge of the optical device substrate when the optical device substrate is rotated on the substrate support and a second actuator operable to apply a force on the holder in a direction towards the substrate support. The second actuator is a constant force actuator.

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

Abstract: A method of processing an optical device is provided, including: positioning an optical device on a substrate support in an interior volume of a process chamber, the optical device including an optical device substrate and a plurality of optical device structures formed over the optical device substrate, each optical device structure including a bulk region formed of silicon carbide and one or more surface regions formed of silicon oxycarbide. The method further includes providing one or more process gases to the interior volume of the process chamber, and generating a plasma of the one or more process gases in the interior volume for a first time period when the optical device is on the substrate support, and stopping the plasma after the first time period. A carbon content of the one or more surface regions of each optical device structure is reduced by at least 50% by the plasma.

Abstract: Embodiments of the present disclosure relate to methods, systems, and apparatus for inkjet printing self-assembled monolayer (SAM) structures on substrates. In one embodiment, which can be combined with other embodiments, one or more SAM layers are printed on a substrate surface of a substrate in a localized manner such that a portion of the substrate surface is left exposed to a processing region of the inkjet chamber. The printing includes spraying one or more subsections of the substrate surface with an ink, the ink having a SAM composition. The SAM composition includes an active component, and a hydrophobic tail.

Abstract: Methods of dicing optical devices from an optical device substrate are disclosed. The methods include disposing a protective coating only over the optical devices. The optical device substrate includes the optical devices disposed on the surface of the optical device substrate with areas therebetween. The areas of the optical device substrate are exposed by the protective coating. The protective coating includes a polymer, a solvent, and an additive. The methods further include curing the protective coating via a cure process so that the protective coating is water-soluble after the solvent is removed by the cure process, dicing the optical devices from the optical device substrate by projecting a laser beam to the areas between the optical devices, and exposing the protective coating to water to remove the protective coating from the optical devices that are diced.

Abstract: A method and apparatus for forming an optical device are described. The optical device is formed by depositing a plurality of ink drops on a surface of a substrate. The plurality of ink drops are contained within a chemical stopper, such that the chemical stopper surrounds each individual ink drop. The chemical stopper is configured to reduce reflow of the ink drops and is a fraction of the height of each of the ink drops. The ink drops are baked after being deposited within the chemical stoppers as liquid ink drops.

Abstract: Methods of curing a deformation in a substrate are provided. In some embodiments, the method includes identifying one or more areas on the substrate with deformation. The method further includes printing a first film on a first area of a surface of the substrate via inkjet printing, the first film being a material that polymerizes and contracts when cured. The method includes printing a second film on a second area of the surface of the substrate via inkjet printing, the second film being a material that polymerizes and contracts when cured. The method further includes curing the first film and the second film to induce a bend in the substrate. In some embodiments, the method includes inkjet printing a third film and a fourth film on the surface of the substrate.

Abstract: A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer.