Patents by Inventor Rami HOURANI

Rami HOURANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220130719
    Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.
    Type: Application
    Filed: January 4, 2022
    Publication date: April 28, 2022
    Inventors: Kevin L. LIN, Robert L. BRISTOL, James M. BLACKWELL, Rami HOURANI, Marie KRYSAK
  • Publication number: 20220102207
    Abstract: Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Inventors: Florian GSTREIN, Rami HOURANI, Gopinath BHIMARASETTI, James M. BLACKWELL
  • Patent number: 11251072
    Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Robert L. Bristol, James M. Blackwell, Rami Hourani, Marie Krysak
  • Publication number: 20220035251
    Abstract: A method of forming a three dimensional feature inwardly of a surface of a material includes providing a droplet dispenser including an outlet configured to dispense discrete droplets of a liquid material having a reactant therein capable of reacting with, and thereby removing, portions of the material layer with which the droplets come into contact, providing a support configured support the material thereon, the support, and the droplet dispenser, movable with respect to one another, such that the outlet of the droplet dispenser is positionable over different discrete areas of the surface of the material, and positioning the surface of the material under the droplet dispenser, and dispensing droplets to discrete portions of the surface of the material in a desired area thereof, to remove at least a portion of the material in the desired area and thereby form a three dimensional recess inwardly of the surface of the material.
    Type: Application
    Filed: September 25, 2020
    Publication date: February 3, 2022
    Inventors: Jinrui GUO, Ludovic GODET, Daihua ZHANG, Kang LUO, Rami HOURANI
  • Publication number: 20220025518
    Abstract: Embodiments of the present disclosure generally relate to methods and materials for optical device fabrication. More specifically, embodiments described herein provide for optical film deposition methods and materials to expand the process window for amorphous optical film deposition via incorporation of dopant atoms by suppressing the crystal growth of optical materials during deposition. By enabling amorphous films to be deposited at higher temperatures, significant cost savings and increased throughput are possible.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 27, 2022
    Inventors: Andrew CEBALLOS, Ludovic GODET, Karl J. ARMSTRONG, Rami HOURANI
  • Publication number: 20220026603
    Abstract: Embodiments of the present disclosure relate to optical device films and methods of forming optical device films. Specifically, embodiments described herein provide for an optical device film having a constant oxygen-concentration, a first concentration profile of the first material, and a second concentration profile of the second material. The first material, described and referenced to herein, has a first refractive index about 2.0 or greater and the second material has a second refractive index less than 2.0.
    Type: Application
    Filed: July 9, 2021
    Publication date: January 27, 2022
    Inventors: Andrew CEBALLOS, Ludovic GODET, Karl J. ARMSTRONG, Rami HOURANI
  • Patent number: 11232980
    Abstract: Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Florian Gstrein, Rami Hourani, Gopinath Bhimarasetti, James M. Blackwell
  • Publication number: 20210397084
    Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Inventors: James M. BLACKWELL, Robert L. BRISTOL, Marie KRYSAK, Florian GSTREIN, Eungnak HAN, Kevin L. LIN, Rami HOURANI, Shane M. HARLSON
  • Publication number: 20210325777
    Abstract: Embodiments of the present disclosure generally relate to optically densified nanoimprint films and processes for making these optically densified nanoimprint films, as well as optical devices containing the optically densified nanoimprint films. In one or more embodiments, a method of forming a nanoimprint film includes positioning a substrate containing a porous nanoimprint film within a processing chamber, where the porous nanoimprint film contains nanoparticles and voids between the nanoparticles, and the porous nanoimprint film has a refractive index of less than 2. The method also includes depositing a metal oxide on the porous nanoimprint film and within at least a portion of the voids to produce an optically densified nanoimprint film during an atomic layer deposition (ALD) process.
    Type: Application
    Filed: December 29, 2020
    Publication date: October 21, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Andrew CEBALLOS, Rami HOURANI, Kenichi OHNO, Yuriy MELNIK, Amita JOSHI
  • Publication number: 20210325778
    Abstract: Embodiments of the present disclosure generally relate to densified nanoimprint films and processes for making these densified nanoimprint films, as well as optical devices containing the densified nanoimprint films. In one or more embodiments, a densified nanoimprint film contains a base nanoimprint film and a metal oxide disposed on the base nanoimprint film and in between the nanoparticles. The base nanoimprint film contains nanoparticles, where the nanoparticles contain titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, hafnium oxide, chromium oxide, indium tin oxide, silicon nitride, or any combination thereof. The metal oxide contains aluminum oxide, titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, indium oxide, indium tin oxide, hafnium oxide, chromium oxide, scandium oxide, tin oxide, zinc oxide, yttrium oxide, praseodymium oxide, magnesium oxide, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.
    Type: Application
    Filed: December 29, 2020
    Publication date: October 21, 2021
    Inventors: Andrew CEBALLOS, Rami HOURANI, Kenichi OHNO, Yuriy MELNIK, Amita JOSHI
  • Patent number: 11137681
    Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, Robert L. Bristol, Marie Krysak, Florian Gstrein, Eungnak Han, Kevin L. Lin, Rami Hourani, Shane M. Harlson
  • Patent number: 11139401
    Abstract: Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Rami Hourani, Elijah Karpov, Prashant Majhi, Ravi Pillarisetty, Abhishek Sharma
  • Publication number: 20210225698
    Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.
    Type: Application
    Filed: March 30, 2021
    Publication date: July 22, 2021
    Inventors: Kevin L. LIN, Richard E. SCHENKER, Jeffery D. BIELEFELD, Rami HOURANI, Manish CHANDHOK
  • Publication number: 20210223686
    Abstract: Embodiments of the present disclosure generally relate to imprint compositions and materials and related processes useful for nanoimprint lithography (NIL). In one or more embodiments, an imprint composition contains one or more types of nanoparticles, one or more surface ligands, one or more solvents, one or more additives, and one or more acrylates.
    Type: Application
    Filed: July 28, 2020
    Publication date: July 22, 2021
    Inventors: Amita JOSHI, Ian Matthew MCMACKIN, Rami HOURANI, Yingdong LUO, Sivapackia GANAPATHIAPPAN, Ludovic GODET
  • Patent number: 11011463
    Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Richard E. Schenker, Jeffery D. Bielefeld, Rami Hourani, Manish Chandhok
  • Publication number: 20210143265
    Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
    Type: Application
    Filed: January 21, 2021
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Scott B. Clendenning, Szuya S. Liao, Florian Gstrein, Rami Hourani, Patricio E. Romero, Grant M. Kloster, Martin M. Mitan
  • Patent number: 10971600
    Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Scott B. Clendenning, Szuya S. Liao, Florian Gstrein, Rami Hourani, Patricio E. Romero, Grant M. Kloster, Martin M. Mitan
  • Publication number: 20210091194
    Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Rami HOURANI, Richard VREELAND, Giselle ELBAZ, Manish CHANDHOK, Richard E. SCHENKER, Gurpreet SINGH, Florian GSTREIN, Nafees KABIR, Tristan A. TRONIC, Eungnak HAN
  • Publication number: 20210091075
    Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Szuya S. LIAO, Scott B. CLENDENNING, Jessica TORRES, Lukas BAUMGARTEL, Kiran CHIKKADI, Diane LANCASTER, Matthew V. METZ, Florian GSTREIN, Martin M. MITAN, Rami HOURANI
  • Publication number: 20210090990
    Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Rami HOURANI, Manish CHANDHOK, Richard E. SCHENKER, Florian GSTREIN, Leonard P. GULER, Charles H. WALLACE, Paul A. NYHUS, Curtis WARD, Mohit K. HARAN, Reken PATEL