Patents by Inventor Rami HOURANI

Rami HOURANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210325777
    Abstract: Embodiments of the present disclosure generally relate to optically densified nanoimprint films and processes for making these optically densified nanoimprint films, as well as optical devices containing the optically densified nanoimprint films. In one or more embodiments, a method of forming a nanoimprint film includes positioning a substrate containing a porous nanoimprint film within a processing chamber, where the porous nanoimprint film contains nanoparticles and voids between the nanoparticles, and the porous nanoimprint film has a refractive index of less than 2. The method also includes depositing a metal oxide on the porous nanoimprint film and within at least a portion of the voids to produce an optically densified nanoimprint film during an atomic layer deposition (ALD) process.
    Type: Application
    Filed: December 29, 2020
    Publication date: October 21, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Andrew CEBALLOS, Rami HOURANI, Kenichi OHNO, Yuriy MELNIK, Amita JOSHI
  • Publication number: 20210325778
    Abstract: Embodiments of the present disclosure generally relate to densified nanoimprint films and processes for making these densified nanoimprint films, as well as optical devices containing the densified nanoimprint films. In one or more embodiments, a densified nanoimprint film contains a base nanoimprint film and a metal oxide disposed on the base nanoimprint film and in between the nanoparticles. The base nanoimprint film contains nanoparticles, where the nanoparticles contain titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, hafnium oxide, chromium oxide, indium tin oxide, silicon nitride, or any combination thereof. The metal oxide contains aluminum oxide, titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, indium oxide, indium tin oxide, hafnium oxide, chromium oxide, scandium oxide, tin oxide, zinc oxide, yttrium oxide, praseodymium oxide, magnesium oxide, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.
    Type: Application
    Filed: December 29, 2020
    Publication date: October 21, 2021
    Inventors: Andrew CEBALLOS, Rami HOURANI, Kenichi OHNO, Yuriy MELNIK, Amita JOSHI
  • Patent number: 11139401
    Abstract: Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Rami Hourani, Elijah Karpov, Prashant Majhi, Ravi Pillarisetty, Abhishek Sharma
  • Patent number: 11137681
    Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: James M. Blackwell, Robert L. Bristol, Marie Krysak, Florian Gstrein, Eungnak Han, Kevin L. Lin, Rami Hourani, Shane M. Harlson
  • Publication number: 20210223686
    Abstract: Embodiments of the present disclosure generally relate to imprint compositions and materials and related processes useful for nanoimprint lithography (NIL). In one or more embodiments, an imprint composition contains one or more types of nanoparticles, one or more surface ligands, one or more solvents, one or more additives, and one or more acrylates.
    Type: Application
    Filed: July 28, 2020
    Publication date: July 22, 2021
    Inventors: Amita JOSHI, Ian Matthew MCMACKIN, Rami HOURANI, Yingdong LUO, Sivapackia GANAPATHIAPPAN, Ludovic GODET
  • Publication number: 20210225698
    Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.
    Type: Application
    Filed: March 30, 2021
    Publication date: July 22, 2021
    Inventors: Kevin L. LIN, Richard E. SCHENKER, Jeffery D. BIELEFELD, Rami HOURANI, Manish CHANDHOK
  • Patent number: 11011463
    Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Richard E. Schenker, Jeffery D. Bielefeld, Rami Hourani, Manish Chandhok
  • Publication number: 20210143265
    Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
    Type: Application
    Filed: January 21, 2021
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Scott B. Clendenning, Szuya S. Liao, Florian Gstrein, Rami Hourani, Patricio E. Romero, Grant M. Kloster, Martin M. Mitan
  • Patent number: 10971600
    Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Scott B. Clendenning, Szuya S. Liao, Florian Gstrein, Rami Hourani, Patricio E. Romero, Grant M. Kloster, Martin M. Mitan
  • Publication number: 20210091075
    Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Szuya S. LIAO, Scott B. CLENDENNING, Jessica TORRES, Lukas BAUMGARTEL, Kiran CHIKKADI, Diane LANCASTER, Matthew V. METZ, Florian GSTREIN, Martin M. MITAN, Rami HOURANI
  • Publication number: 20210090990
    Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Rami HOURANI, Manish CHANDHOK, Richard E. SCHENKER, Florian GSTREIN, Leonard P. GULER, Charles H. WALLACE, Paul A. NYHUS, Curtis WARD, Mohit K. HARAN, Reken PATEL
  • Publication number: 20210091194
    Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Rami HOURANI, Richard VREELAND, Giselle ELBAZ, Manish CHANDHOK, Richard E. SCHENKER, Gurpreet SINGH, Florian GSTREIN, Nafees KABIR, Tristan A. TRONIC, Eungnak HAN
  • Publication number: 20210057337
    Abstract: Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.
    Type: Application
    Filed: March 26, 2018
    Publication date: February 25, 2021
    Inventors: Eungnak HAN, Tayseer MAHDI, Rami HOURANI, Gurpreet SINGH, Florian GSTREIN
  • Publication number: 20210013145
    Abstract: Etch stop layer-based approaches for via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer, wherein each of the plurality of conductive lines has a bulk portion including a metal and has an uppermost surface including the metal and a non-metal. A hardmask layer is on the plurality of conductive lines and on an uppermost surface of the ILD layer, and includes a first hardmask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hardmask component on and aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of one of the plurality of conductive lines, the portion having a composition different than the uppermost surface including the metal and the non-metal.
    Type: Application
    Filed: March 28, 2018
    Publication date: January 14, 2021
    Inventors: Florian GSTREIN, Cen TAN, Rami HOURANI
  • Patent number: 10892184
    Abstract: Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Kevin L. Lin, James M. Blackwell, Rami Hourani, Eungnak Han
  • Patent number: 10886175
    Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Eungnak Han, Rami Hourani, Florian Gstrein, Gurpreet Singh, Scott B. Clendenning, Kevin L. Lin, Manish Chandhok
  • Publication number: 20200402917
    Abstract: Disclosed herein are IC structures, packages, and devices that include recesses processed via selective growth. An example integrated circuit (IC) structure, includes a first dielectric material, a second dielectric material on the first dielectric material, and a recess in the second dielectric material, wherein the recess includes a bottom, a top, and sidewalls. The IC further includes a first material within the recess and at a bottom of the recess, wherein the first material includes a metal and oxygen, a self-assembled monolayer (SAM) material, or an organic material, and a second material within the recess and between the first material and the top of the recess, wherein the second material is in contact with the sidewalls of the recess.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: Kevin L. Lin, Nafees A. Kabir, James Munro Blackwell, Rami Hourani
  • Publication number: 20200388711
    Abstract: Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memtory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Brian Doyle, Rami Hourani, Elijah Karpov, Prashant Majhi, Ravi Pillarisetty, Abhishek Sharma
  • Patent number: 10756215
    Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Grant Kloster, Scott B. Clendenning, Rami Hourani, Szuya S. Liao, Patricio E. Romero, Florian Gstrein
  • Patent number: 10672650
    Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.
    Type: Grant
    Filed: February 18, 2018
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Rami Hourani, Marie Krysak, Florian Gstrein, Ruth A. Brain, Mark T. Bohr