Patents by Inventor Raminda U. Madurawe

Raminda U. Madurawe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210168312
    Abstract: Implementations of a pixel may include at least one photodiode coupled with a floating diffusion; a first metal-insulator-metal (MIM) capacitor including a first electrode and a second electrode; and a second MIM capacitor coupled in parallel with the first MIM capacitor, the second MIM capacitor including a first electrode and a second electrode. The first MIM capacitor and second MIM capacitor may be coupled with the floating diffusion.
    Type: Application
    Filed: November 23, 2020
    Publication date: June 3, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Raminda U. MADURAWE, Irfan RAHIM
  • Patent number: 9087169
    Abstract: An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs; and selecting a metal tab from a first set of selectable metal tabs for a first data value, or a second set of selectable metal tabs for a second data value for each of the fixed metal tabs; wherein a first set metal tab and a second set metal tab couples each said fixed metal tab to first and second voltages respectively.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: July 21, 2015
    Inventors: Raminda U. Madurawe, Thomas H. White
  • Patent number: 8810276
    Abstract: A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: August 19, 2014
    Inventor: Raminda U. Madurawe
  • Patent number: 7129744
    Abstract: A programmable interconnect structure for an integrated circuit comprises: a pass-gate fabricated on a substrate layer to electrically connect a first node to a second node; and a configuration circuit including at least one memory element to control said pass-gate fabricated substantially above said substrate layer; and a programmable method to select between isolating said first and second nodes and connecting said first and second nodes. A programmable buffer structure for an integrated circuit comprises: a first and a second terminal; and a programmable pull-up and a programmable pull-down circuit coupled between said first and second terminals; and a configuration circuit including at least one memory element coupled to said pull-up and pull-down circuits; and a programmable method to select between isolating said first terminal from second terminal by deactivating said pull-up and pull-down circuits, and coupling said first terminal to second terminal by activating said pull-up and pull-down circuits.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: October 31, 2006
    Assignee: Viciciv Technology
    Inventor: Raminda U. Madurawe
  • Patent number: 7071104
    Abstract: A technique to form a structure with a rough topography in a planarized semiconductor process. The rough topography is formed by creating cored contacts. Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: July 4, 2006
    Assignee: Altera Corporation
    Inventor: Raminda U. Madurawe
  • Patent number: 7018875
    Abstract: A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor Gated-FET device comprises a lightly doped resistive channel region formed on a first semiconductor thin film layer; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: March 28, 2006
    Assignee: Viciciv Technology
    Inventor: Raminda U. Madurawe
  • Patent number: 6972234
    Abstract: A method of fabricating CMOS devices suitable for high voltage and low voltage applications, while maintaining minimum channel lengths for the devices. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants (120), enhancement implants (130), and wells (140) are all formed using a single mask.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: December 6, 2005
    Assignee: Altera Corporation
    Inventors: Raminda U. Madurawe, David K. Y. Liu
  • Patent number: 6855988
    Abstract: A switching device for integrated circuit applications is disclosed. A first switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. Said first and second devices are constructed as complementary Gated-FET devices, wherein the conductive path of a Gated-FET comprises a resistive channel of the same dopant type as source and drain regions. A second switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. The conductive paths of said first and second devices are comprised of a single geometry of a semiconductor material.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: February 15, 2005
    Assignee: Viciciv Technology
    Inventor: Raminda U. Madurawe
  • Patent number: 6828620
    Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: December 7, 2004
    Assignee: Altera Corporation
    Inventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
  • Patent number: 6828689
    Abstract: A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed. In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak access device constructed in a semiconductor thin film layer located vertically above the strong devices. The strong devices are used in the data read and write paths, and the weak devices are used for latch feed-back and sector data erase. This first embodiment is used for high density and high speed memory applications. In a second embodiment, an SRAM cell comprises thin film inverters and thin film access devices constructed in a semiconductor thin film layer located substantially above logic transistors. The TFT SRAM cell is buried above the logic gates of an Integrated Circuit to consume no extra Silicon real estate. This second embodiment is used for slow access and Look-Up-Tables type memory applications.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: December 7, 2004
    Assignee: VI CI CIV
    Inventor: Raminda U. Madurawe
  • Patent number: 6803804
    Abstract: A latch includes an inverter; a pass transistor having a first terminal coupled to an input of the inverter and a second terminal coupled to a programming voltage; a first capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a first predetermined voltage; and a second capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a second predetermined voltage; wherein each of the first and second capacitors uses an antifuse.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: October 12, 2004
    Inventor: Raminda U. Madurawe
  • Patent number: 6781883
    Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: August 24, 2004
    Assignee: Altera Corporation
    Inventors: Raminda U. Madurawe, Myron W. Wong, John C. Costello, James D. Sansbury, Bruce E. Mielk
  • Publication number: 20040152245
    Abstract: A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor Gated-FET device comprises a lightly doped resistive channel region formed on a first semiconductor thin film layer; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.
    Type: Application
    Filed: January 23, 2004
    Publication date: August 5, 2004
    Inventor: Raminda U. Madurawe
  • Patent number: 6747478
    Abstract: A three-dimensional semiconductor device with two selectable manufacturing configurations includes a first module layer having a plurality of circuit blocks; and a second module layer formed substantially above the first module layer, wherein in a first selectable configuration a plurality of memory circuits are formed to store instructions to control a portion of the circuit blocks, and wherein in a second selectable configuration a predetermined conductive pattern is formed in lieu of the memory circuit to control substantially the same portion of the circuit blocks.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: June 8, 2004
    Assignee: Viciciv
    Inventor: Raminda U. Madurawe
  • Patent number: 6713839
    Abstract: An antifuse includes a grid having at least one n-well active stripe and at least one polysilicon stripe; a first oxide layer having a first oxide thickness, the first oxide layer adapted to electrically short the n-well active stripe with the polysilicon stripe; and a second oxide layer surrounding the first oxide and thicker than the first oxide layer.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: March 30, 2004
    Assignee: AirIP
    Inventor: Raminda U. Madurawe
  • Publication number: 20040018711
    Abstract: A method for forming a semiconductor device includes fabricating one or more digital circuits on a substrate; selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to control portion of digital circuits; and fabricating an interconnect and routing layer substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern.
    Type: Application
    Filed: October 8, 2002
    Publication date: January 29, 2004
    Inventor: Raminda U. Madurawe
  • Publication number: 20040004298
    Abstract: A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed. In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak access device constructed in a semiconductor thin film layer located vertically above the strong devices. The strong devices are used in the data read and write paths, and the weak devices are used for latch feed-back and sector data erase. This first embodiment is used for high density and high speed memory applications. In a second embodiment, an SRAM cell comprises thin film inverters and thin film access devices constructed in a semiconductor thin film layer located substantially above logic transistors. The TFT SRAM cell is buried above the logic gates of an Integrated Circuit to consume no extra Silicon real estate. This second embodiment is used for slow access and Look-Up-Tables type memory applications.
    Type: Application
    Filed: April 14, 2003
    Publication date: January 8, 2004
    Inventor: Raminda U. Madurawe
  • Publication number: 20040004251
    Abstract: A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor Gated-FET device comprises a lightly doped resistive channel region formed on a first semiconductor thin film layer; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.
    Type: Application
    Filed: April 14, 2003
    Publication date: January 8, 2004
    Inventor: Raminda U. Madurawe
  • Publication number: 20040004252
    Abstract: A switching device for integrated circuit applications is disclosed. A first switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. Said first and second devices are constructed as complementary Gated-FET devices, wherein the conductive path of a Gated-FET comprises a resistive channel of the same dopant type as source and drain regions. A second switching device includes a first device between a first voltage supply and a common output, a second device between a second voltage supply and common output, and a common input to control said first and second devices. The conductive paths of said first and second devices are comprised of a single geometry of a semiconductor material.
    Type: Application
    Filed: April 14, 2003
    Publication date: January 8, 2004
    Inventor: Raminda U. Madurawe
  • Publication number: 20040004496
    Abstract: A three-dimensional semiconductor device with two selectable manufacturing configurations includes a first module layer having a plurality of circuit blocks; and a second module layer formed substantially above the first module layer, wherein in a first selectable configuration a plurality of memory circuits are formed to store instructions to control a portion of the circuit blocks, and wherein in a second selectable configuration a predetermined conductive pattern is formed in lieu of the memory circuit to control substantially the same portion of the circuit blocks.
    Type: Application
    Filed: October 8, 2002
    Publication date: January 8, 2004
    Inventor: Raminda U. Madurawe