Patents by Inventor Raminda U. Madurawe
Raminda U. Madurawe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040004251Abstract: A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor Gated-FET device comprises a lightly doped resistive channel region formed on a first semiconductor thin film layer; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.Type: ApplicationFiled: April 14, 2003Publication date: January 8, 2004Inventor: Raminda U. Madurawe
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Publication number: 20030218487Abstract: A latch includes an inverter; a pass transistor having a first terminal coupled to an input of the inverter and a second terminal coupled to a programming voltage; a first capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a first predetermined voltage; and a second capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a second predetermined voltage; wherein each of the first and second capacitors uses an antifuse.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Inventor: Raminda U. Madurawe
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Publication number: 20030218234Abstract: An antifuse includes a grid having at least one n-well active stripe and at least one polysilicon stripe; a first oxide layer having a first oxide thickness, the first oxide layer adapted to electrically short the n-well active stripe with the polysilicon stripe; and a second oxide layer surrounding the first oxide and thicker than the first oxide layer.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Inventor: Raminda U. Madurawe
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Patent number: 6646919Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.Type: GrantFiled: June 4, 2001Date of Patent: November 11, 2003Assignee: Altera CorporationInventors: Raminda U. Madurawe, Myron W. Wong, John C. Costello, James D. Sansbury, Bruce F. Mielke
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Publication number: 20030197218Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.Type: ApplicationFiled: May 12, 2003Publication date: October 23, 2003Applicant: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6624467Abstract: Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.Type: GrantFiled: July 9, 2002Date of Patent: September 23, 2003Assignee: Altera CorporationInventors: Peter J. McElheny, Raminda U. Madurawe, Richard G. Smolen, Minchang Liang
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Patent number: 6624524Abstract: A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in order to augment nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.Type: GrantFiled: October 18, 1999Date of Patent: September 23, 2003Assignee: Altera CorporationInventor: Raminda U. Madurawe
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Patent number: 6573138Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.Type: GrantFiled: July 8, 1999Date of Patent: June 3, 2003Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
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Patent number: 6532170Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (810). In one embodiment, the programmable memory element (810) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 2, 2001Date of Patent: March 11, 2003Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6472272Abstract: Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.Type: GrantFiled: December 8, 2000Date of Patent: October 29, 2002Assignee: Altera CorporationInventors: Peter J. McElheny, Raminda U. Madurawe, Richard G. Smolen, Minchang Liang
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Patent number: 6417550Abstract: A transistor device suitable for high voltage and low voltage applications, while maintaining minimum channel lengths. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants (120), enhancement implants (130), and wells (140) are all formed using a single mask.Type: GrantFiled: August 29, 1997Date of Patent: July 9, 2002Assignee: Altera CorporationInventors: Raminda U. Madurawe, David K. Y. Liu
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Patent number: 6366498Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 30, 1999Date of Patent: April 2, 2002Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Publication number: 20020020891Abstract: A method of fabricating CMOS devices suitable for high voltage and low voltage applications, while maintaining minimum channel lengths for the devices. In one embodiment, pocket implants (310) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants (120), enhancement implants (130), and wells (140) are all formed using a single mask.Type: ApplicationFiled: August 29, 1997Publication date: February 21, 2002Inventors: RAMINDA U. MADURAWE, DAVID K. Y. LIU
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Patent number: 6295230Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: August 30, 1999Date of Patent: September 25, 2001Assignee: Altera CoporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6268623Abstract: Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage.Type: GrantFiled: December 22, 1997Date of Patent: July 31, 2001Assignee: Altera CorporationInventors: Raminda U. Madurawe, Myron W. Wong, John C. Costello, James D. Sansbury, Bruce E. Mielke
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Patent number: 6265746Abstract: Provided is a high resistance value vertically-integrated semiconductor interconnect with resistance in the 10 k&OHgr;-10 G&OHgr; range, and a process to make such highly resistive interconnects together with low resistive interconnects in a precisely controllable manner. In addition, provided is an SRAM cell with highly resistive contact processing for a pull-up resistor.Type: GrantFiled: January 8, 1999Date of Patent: July 24, 2001Assignee: Altera CorporationInventors: Raminda U. Madurawe, Charu Sardana, Peter J. McElheny, Richard G. Smolen
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Patent number: 6226201Abstract: A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).Type: GrantFiled: October 13, 1998Date of Patent: May 1, 2001Assignee: Altera CorporationInventors: Raminda U. Madurawe, James D. Sansbury
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Patent number: 6187634Abstract: Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.Type: GrantFiled: March 19, 1998Date of Patent: February 13, 2001Assignee: Altera CorporationInventors: Peter J. McElheny, Raminda U. Madurawe, Richard G. Smolen, Minchang Liang
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Patent number: 6127217Abstract: Provided is a high resistance value vertically-integrated semiconductor interconnect, and a process to make such highly resistive interconnects together with low resistive interconnects in a precisely controllable manner. In addition, provided is an SRAM cell with highly resistive contact processing for a pull-up resistor.Type: GrantFiled: January 8, 1999Date of Patent: October 3, 2000Assignee: Altera CorporationInventors: Raminda U. Madurawe, Charu Sardana, Peter J. McElheny, Richard G. Smolen
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Patent number: 6122209Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.Type: GrantFiled: July 8, 1999Date of Patent: September 19, 2000Assignee: Altera CorporationInventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright