Patents by Inventor Randall Cher Laing Cha

Randall Cher Laing Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020132448
    Abstract: A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.
    Type: Application
    Filed: March 14, 2001
    Publication date: September 19, 2002
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yeow Kheng Lim, Randall Cher Laing Cha, Alex See, Tae Jong Lee, Wang Ling Goh