Abstract: A memory controller, upon detecting an interval of inactivity (that is, no read or write access from a processor or I/O devices with respect to main storage or memory SDRAMs) halts external refresh commands from the processor, and initiates STR mode in main storage to preserve data contents in the memory SDRAMs and to save energy. Then, upon detecting a read or write operation, the memory controller signals main storage to exit STR mode.

Abstract: A storage controller, upon detecting an interval of storage inactivity, inhibits external storage refresh commands and places the storage in self timed refresh (STR) mode. Upon detecting storage activity while storage is in STR mode, the controller terminates STR mode in storage. Upon detecting a scrub request while storage is in STR mode, the controller terminates STR mode in the storage and thereafter services the scrub request. Upon completing execution of the scrub request, the controller returns storage to STR mode.

Abstract: A memory arrangement, where a memory control logic, which drives a memory array, is maintained in a volatile power domain, and clock redrive circuitry, address control redrive circuitry, data transceiver, and the memory array itself are all maintained in a non-volatile power domain, in order to increase the effective life time of a battery backup system. The memory arrangement includes buffering circuitry to prevent leakage currents, and the appropriate control of nets between the memory control logic and the memory array, in order to avoid additional sources of leakage current and bus driver contentions.